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* x86: Enable SPI flash support for corebootSimon Glass2013-03-19-3/+9
| | | | | | Turn on SPI flash support and related commands. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add FDT SPI node for linkSimon Glass2013-03-19-0/+11
| | | | | | Add a memory-mapped 8GB SPI chip. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move PCI init before SPI initSimon Glass2013-03-19-4/+4
| | | | | | | It is possible that our PCI bus will provide the SPI controller, so change the init order to make this work. Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Enable FDT-based configuration and memory mappingSimon Glass2013-03-19-1/+48
| | | | | | | Enable device tree control of SPI flash, and use this to implement memory-mapped SPI flash, which is supported on Intel chips. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Set maximum write size for ICHSimon Glass2013-03-19-0/+5
| | | | | | | This SPI controller can only write 64 bytes at a time. Add this restriction in so that 'sf write' works correct for blocks larger than 64 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Respect maximum SPI write sizeSimon Glass2013-03-19-2/+8
| | | | | | | | Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of bytes that can be in a write transaction. Support this by breaking the writes into multiple transactions. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Add parameter for maximum write sizeSimon Glass2013-03-19-0/+3
| | | | | | | | Some SPI controllers (e.g. Intel ICH) have a limit on the number of SPI bytes that can be written at a time. Add this as a parameter so that clients of the SPI interface can respect this value. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Add Intel ICH driverSimon Glass2013-03-19-0/+893
| | | | | | | | | | | | | | | | | | This supports Intel ICH7/9. The Intel controller is a little unusual in that it is mostly intended for use with SPI flash, and has some optimisations and features specifically for that application. In particular it is not possible to support ongoing transactions that continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END. This driver supports writes of up to 64 bytes at a time, the limit for the controller. Future work will improve this. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Use spi_flash_alloc() in each SPI flash driverSimon Glass2013-03-19-52/+8
| | | | | | | | Rather than each device having its own way to allocate a SPI flash structure, use the new allocation function everywhere. This will make it easier to extend the interface without breaking devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Add spi_flash_alloc() to create a new SPI flash structSimon Glass2013-03-19-0/+63
| | | | | | | | | | At present it is difficult to extend the SPI flash structure since all devices allocate it themselves, and few of them zero all fields. Add a new function spi_flash_alloc() which can be used by SPI devices to perform this allocation, and thus ensure that all devices can better cope with SPI structure changes. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Use spi_alloc_slave() in each SPI driverSimon Glass2013-03-19-83/+36
| | | | | | | | Rather than each driver having its own way to allocate a SPI slave, use the new allocation function everywhere. This will make it easier to extend the interface without breaking drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Add function to allocate a new SPI slaveSimon Glass2013-03-19-0/+83
| | | | | | | | | | At present it is difficult to extend the SPI structure since all drivers allocate it themselves, and few of them zero all fields. Add a new function spi_alloc_slave() which can be used by SPI drivers to perform this allocation, and thus ensure that all drivers can better cope with SPI structure changes. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add fdtdec_get_addr_size() to read reg propertiesSimon Glass2013-03-19-6/+36
| | | | | | | | It is common to have a "reg = <address size>" property in the FDT. Add a function to handle this, similar to the existing fdtdec_get_addr(); Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-03-18-10407/+15588
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-1570/+2881
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| | * Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-14/+292
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: fdt: Move aliases from dtsi to dts file as per other TegrasTom Warren2013-03-14-8/+8
| | | | | | | | | | | | | | | | | | | | | All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bitsTom Warren2013-03-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux code issues a warning if the caller attempts to disable the lock bit in a pinmux register, since this is impossible (once it's locked, the only way to unlock it is to reset the device/pmt controller). The I2C/DDC/CEC/USB macros expect a lock setting to be passed in, and the previous setting of DISABLE caused the pinmux table parsing code to issue the warning. Changing the lock bits in these table entries to DEFAULT (i.e. don't touch it) fixes this. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: Fix/update GP padcfg register structTom Warren2013-03-14-8/+26
| | | | | | | | | | | | | | | | | | | | | Differences in padcfg registers (some removed, some added) between Tegra30 and Tegra114 weren't picked up when I first ported this file. Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entryTom Warren2013-03-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register. Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: enable a common set of disk-related commands everywhereStephen Warren2013-03-14-80/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable a common set of partition types, filesystems, and related commands in tegra-common.h, so that they are available on all Tegra boards. This allows boot.scr (loaded and executed by the default built-in environment) on those boards to assume that certain features are always available. Do this in tegra-common.h, so that individual board files can undefine the features if they really don't want any of them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * disk: define HAVE_BLOCK_DEVICE if CONFIG_CMD_PARTStephen Warren2013-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various code that is conditional upon HAVE_BLOCK_DEVICE is required by code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if CONFIG_CMD_PART is enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * disk: define HAVE_BLOCK_DEVICE in a common placeStephen Warren2013-03-14-40/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This set of ifdefs is used in a number of places. Move its definition somewhere common so it doesn't have to be repeated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: make bounce buffer option commonStephen Warren2013-03-14-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to tegra-common.h to ensure it's always set. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * Tegra30: MMC: Enable DT MMC driver support for Tegra30 Cardhu boardsTom Warren2013-03-14-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load a kernel off of an SD card OK, card detect works, and the env is now stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driverTom Warren2013-03-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra30 SD/MMC controller differs enough from Tegra20 that it needs its own entry in the compat_names/compat_id tables and in the Tegra MMC driver. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.Tom Warren2013-03-14-8/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routinesTom Warren2013-03-14-1/+81
| | | | | | | | | | | | | | | | | | | | | T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30Tom Warren2013-03-14-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | Removed SDMMC base addresses from tegra.h since they're no longer used. Added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+47
| | | | | | | | | | | | | | | | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-5/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-377/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: Cardhu: Remove unneeded cardhu.c.mmc fileTom Warren2013-03-14-151/+0
| | | | | | | | | | | | | | | | | | | | | | | | This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)Tom Warren2013-03-14-1/+18
| | | | | | | | | | | | | | | | | | | | | Minor edit to tegra_car node, add gpio node. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY defineTom Warren2013-03-14-5/+3
| | | | | | | | | | | | | | | | | | | | | This wasn't used anywhere in any Tegra build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCsTom Warren2013-03-14-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * ARM: tegra: implement WAR for Tegra114 CPU reset vectorStephen Warren2013-03-14-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-34/+61
| | | | | | | | | | | | | | | | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT filesTom Warren2013-03-14-2/+0
| | | | | | | | | | | | | | | | | | | | | Not used, and wrong in Cardhu's case Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-208/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT filesTom Warren2013-03-14-12/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: tamonten: Add common tamonten.dtsi file from linuxTom Warren2013-03-14-3/+492
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Change /include/ to #include for C preprocessorTom Warren2013-03-14-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: I2C: Enable I2C driver on Dalmore E1611 eval boardTom Warren2013-03-14-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Tested all 5 'buses', i2c probe enumerates device addresses on bus 0, 1 and 2. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
| | * Tegra114: fdt: Update DT files with I2C info for T114/DalmoreTom Warren2013-03-14-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: I2C: Add T114 clock support to tegra_i2c driverTom Warren2013-03-14-5/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
| | * Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to workTom Warren2013-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives). This is needed so that the SDIO slot power can be brought up for the MMC driver, so it has to precede those commits. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]Lucas Stach2013-03-14-87/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ehci_hcd entry points were just calling into the Tegra USB functions. Now that they are in the same file we can just move over the implementation. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * tegra: usb: move implementation into right directoryLucas Stach2013-03-14-560/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * tegra: usb: various small cleanupsLucas Stach2013-03-14-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unneeded headers, function prototype and stale comment, that doesn't match the actual codebase anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-09 20:45:20 +0000