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* arm: bugfix: replace ble with blo in start.S filesAlbert Aribaud2010-10-11-68/+67
| | | | | | | | | | | Generalized misuse of ble within relocation and bss initialization loops caused one iteration too many. Instead of ble ('branch if lower or equal'), use blo ('branch if lower'). While we're at it, fix all 'addreee' typos. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* Merge branch 'at91' of git://git.denx.de/u-boot-atmelWolfgang Denk2010-10-11-74/+90
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| * at91: Add arch_preboot_os which disables PIT in a faster wayAlexander Stein2010-10-05-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | When disabled the PIT runs until it reaches the CPIV value. The Linux PIT driver stops the PIT and waits until it stopped. This can take over 100ms. Simply stopping in u-boot isn't sufficient as the PIT will still be running when Linux is waiting until it stopped. So, we stop it in u-boot by setting the compare value to a value slightly greater than the current running counter to make the PIT stopped in short time. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
| * atmel_usart: change register access to C structureAndreas Bießmann2010-10-05-46/+46
| | | | | | | | | | | | | | This patch introduces C structure definition for register footprint of atmel's usart. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
| * at91_emac.h: fix typo in register definitionAndreas Bießmann2010-10-05-1/+1
| | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig <js_at_ng@scharsoft.de>
| * AT91: convert cpu.c to struct SoC accessReinhard Meyer2010-10-05-20/+12
| | | | | | | | Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
| * at91_emac.c: poll for IDLE when writing PHYAndreas Bießmann2010-10-05-2/+14
| | | | | | | | | | | | | | This patch replaces the unnecessary waiting in at91emac_read() and at91emac_write() by checking the IDLE flag. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * at91_emac.c: fix 'Warning: eth device name has a space!'Andreas Bießmann2010-10-05-5/+1
| | | | | | | | | | | | | | This patch also removes conditional nameing of at91_emac driver whether it's connection to PHY is RMII or MII. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-10-11-153/+1510
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| * | MX51: Support for TTECH vision2 boardStefano Babic2010-10-07-0/+1212
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for TTECH vision2 board. The board has 512MB RAM, SDHC slot and 4MB SPI device from StMicron. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MX51: Register definitions cannot be included in board config fileStefano Babic2010-09-30-4/+6
| | | | | | | | | | | | | | | | | | | | | Due to wrong dependencies, it is not possible to include imx_regs.h inside the board configuration file. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51Stefano Babic2010-09-30-41/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The actual SPI driver for i.MX31 and i.MX51 controller use a wrong byte ordering, because it is supposed to work only with Freescale's devices, as the Power Controllers (PMIC). The driver is not suitable for general purposes, because the buffers passed to spi_xfer must be 32-bit aligned, as it is used mainly to send integer to PMIC devices. The patch drops any kind of limitation and makes the driver useful with devices controlled sending commands composed by single bytes (or by a odd number of bytes), such as spi flash, sensor, etc. Because the byte ordering is changed, any current driver using this controller must be adapted, too. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MXC: Correct SPI_CPOL setting in SPI driverStefano Babic2010-09-30-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic. Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: David Jander <david.jander@protonic.nl>
| * | MX51: Drop unused header file for mx51evkStefano Babic2010-09-29-52/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | As stated in 272017853339f5b9685f9488bdaf5405812d12a4, the mx51evk has not CPLD and all references must be removed. This patch drop a .h file that still remains in board directory. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MXC: Add watchdog support to serial driverStefano Babic2010-09-29-2/+5
| | | | | | | | | | | | | | | | | | | | | Calls WATCHDOG_RESET() inside serial driver for boards enabling watchdog. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MX51: add structure to access System Reset ControllerStefano Babic2010-09-29-0/+10
| | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | MX51: Added pins definition to set up padsStefano Babic2010-09-29-0/+44
| | | | | | | | | | | | | | | | | | | | | Add pins definitions to set up RAM pads. Pins have only a pad, there is no entry in the multiplexer. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | ARM: Use syslib functions for all CORTEXA8Stefano Babic2010-09-29-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The OMAP3 cpu directory contains a syslib file with some utilities that can be shared by all targets using arm cortexa8 processors, not only OMAP. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | Use common function to set GPIOs for MX3 and MX5Stefano Babic2010-09-29-67/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for setting gpios to the MX51 processor and change name to the corresponding functions for MX31. In this way, it is possible to get rid of nasty #ifdef switches related to the processor type. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Wolfgang Denk2010-10-11-702/+668
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| * | | x86: Implement fully relocatable imageGraeme Russ2010-10-07-24/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot.bin can be loaded at any 4-byte aligned memory location and directly 'jumped' to using the 'go' command using the load address as the start address. Doing so performs a 'warm boot' which skips memory initialisation and other low-level initialisations, relocates U-Boot to upper memory and starts U-Boot in RAM as per normal 'cold boot'
| * | | x86: Use loops instead of memcpy/memset in board_init_fGraeme Russ2010-10-07-17/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a small speed increase and prepares for fully relocatable image. Downside is the TEXT_BASE, bss, load address etc must ALL be aligned on a a 4-byte boundary which is not such a terrible restriction as everything is already 4-byte aligned anyway
| * | | x86: Rearrange linker scriptGraeme Russ2010-10-07-23/+21
| | | | | | | | | | | | | | | | Tidy up the linker script and discard some sections to save space
| * | | x86: Rename linker script symbolsGraeme Russ2010-10-07-36/+33
| | | | | | | | | | | | | | | | Create more generic names for the symbols exported from the linker script
| * | | x86: Set cold/warm boot flagGraeme Russ2010-10-07-16/+13
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| * | | x86: Place global data below stack before entering CGraeme Russ2010-10-07-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By reserving space for the Global Data immediately below the stack during assembly level initialisation, the C declaration of the static global data can be removed, along with the 'RAM Bootstrap' function. This results in cleaner code, and the ability to pass boot-up flags from assembler into C
| * | | x86: Dont clobber %eax after getting memory sizeGraeme Russ2010-10-07-3/+2
| | | | | | | | | | | | | | | | By using another register, reduce code size by one instruction
| * | | x86: Don't clobber %ebxGraeme Russ2010-10-07-7/+12
| | | | | | | | | | | | | | | | %ebx will hold low-level boot flags and must be preserved
| * | | x86: Remove usage of %ebp as a return pointerGraeme Russ2010-10-07-13/+12
| | | | | | | | | | | | | | | | Using %ebp as a return pointer prevents creating 'load anywhere' images
| * | | x86: Move ECC initialisation outside RAM initialisationGraeme Russ2010-10-07-14/+14
| | | | | | | | | | | | | | | | | | | | To allow for 'load anywhere' images, the %ebp return pointer 'hack' must be removed, so we cannot have two 'calls' to get_mem_size
| * | | x86: Remove progress indication in low-level initGraeme Russ2010-10-07-54/+2
| | | | | | | | | | | | | | | | | | | | Progress indication is not relocation friendly so remove it in preperation for full relocatability support
| * | | x86: Fix %ss and %esp in register structure for interruptsGraeme Russ2010-10-07-4/+45
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| * | | x86: Change compiler optionsGraeme Russ2010-10-07-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change to: - reparam=3 - no-from-pointer - no-stack-protector - preferred-stack-boundary=2 - no-top-level-reorder These options make the code a little smaller and faster
| * | | x86: Coding Style CleanupGraeme Russ2010-10-07-373/+362
| | | | | | | | | | | | | | | | Perform some basic code cleanups of the x86 files
| * | | x86: Move loading of GTD to C codeGraeme Russ2010-10-07-96/+57
| | | | | | | | | | | | | | | | | | | | Linux has C macros and code to load the GTD after switching to Protected Mode. Using these greatly simplifies the assembler code
| * | | x86: use gc sections to reduce image sizeGraeme Russ2010-10-07-5/+8
| | | | | | | | | | | | | | | | | | | | Follow the discussion of Charles Manning and Mike Frysinger. Using gc_sections helps reduce image size.
| * | | x86: zboot updateGraeme Russ2010-10-07-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | The header of recent Linux Kernels includes the size of the image, and therefore is not needed to be passed to zboot. Still process the third parameter (size of image) in the event that an older kernel is being loaded
| * | | x86: Use TEXT_BASE in linker scriptsGraeme Russ2010-10-07-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Use TEXT_BASE rather than a hard-coded base address on x86 linker scripts. This will allow any board to define its base link address without having to modify the linker script
| * | | x86: Make CONFIG_RELOC_FIXUP_WORKS generic for all x86 boardsGraeme Russ2010-10-07-2/+2
| | | | | | | | | | | | | | | | | | | | Relocation is not board-specific for the x86 architectrure, so CONFIG_RELOC_FIXUP_WORKS can be defined globally in the config.h
| * | | x86: Remove bi_env from do_bdinfoGraeme Russ2010-10-07-1/+0
| | |/ | |/| | | | | | | | | | Commit 55e97429d1e6cf0976711e4e0f29ea924b7e5917 removed the definition from /arch/i386/include/asm/u-boot.h but not its usage in do_bdinfo()
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-10-11-42/+225
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| * | | fsl: add support for NXID v1 EEPROM formatTimur Tabi2010-10-07-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale application note AN3638 describes an update to the NXID format, which stores MAC addresses and related data on an on-board EEPROM. The new version adds support for up to 23 MAC addresses, instead of just 8. Since the initial implementation of NXID had a "0" in the 'version' field, this new version is called "v1". Boards that are shipped with EEPROMs in the NXID v1 format should define CONFIG_SYS_I2C_EEPROM_NXID_1 instead of CONFIG_SYS_I2C_EEPROM_NXID. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: fix rev.2 job queue LIODN error stormKim Phillips2010-10-07-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pumping line-rate traffic though a p4080 rev.2, which is configured to encrypt packets prior to forwarding through an IPsec tunnel, gets this error: of_platform ffe302000.jq: DECO: desc idx 22: LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the "shared from" DECO's Descriptor required that the SEQ LIODNs be the same and they aren't. Since high traffic rates cause DECOs to begin to start sharing shared descriptors amongst themselves, and DECOs inherit job queue LIODNs when accessing shared descriptors, and a recently discovered rev.2 h/w erratum requires all sharing job queues in a partition have same liodn assignment, reassign the first job queue's liodn assignment to the rest. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/p4080: Add new CPC register - HDBCR0Kumar Gala2010-10-07-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Add support for 4th PCI controller on corenet_dsKumar Gala2010-10-07-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We configure the controller but dont have virtual address space thus any devices on the 4th controller are not accessible in u-boot. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/corenet_ds: Various updates to initial env cfgEmil Medve2010-10-07-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Make the U-Boot update command sequence conditional. Helps prevent accidental erasing if an upload or previous step fails * Make it easier to update other FLASH banks * Enable DDR controller cache line interleaving and bank cs0/cs1 by default Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl: verify writes to the MAC address EEPROMTimur Tabi2010-10-07-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code which writes to the on-board EEPROM so that it can detect if the write failed because the EEPROM is write-protected. Most of the 8xxx-class Freescale reference boards use an AT24C02 EEPROM to store MAC addresses and similar information. With this patch, if the EEPROM is protected, the "mac save" command will display an error message indicating that the write has not succeeded. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | p1022ds: add audclk hwconfig setting to enable codec reference clockTimur Tabi2010-10-07-9/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference clock for the audio codec, but by default both are disabled. Add a 'audclk' hwconfig option that allows the user to choose which clock he wants. The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48, 64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and 88200Hz. Also configure a pin muxing to select some SSI signals, which will disable I2C1. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc8569mds: fix some ddr settingsHaiying Wang2010-10-07-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable half drive strength, set RTT to 60Ohm and set write leveling override. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc8569mds: fix consuming long time while relocating code.Haiying Wang2010-10-07-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code maps boot flash as non-cacheable region. When calling relocate_code in flash to copy u-boot from flash to ddr, every loop copy command is read from flash. The flash read speed will be the bottleneck, which consuming long time to do this operation. To resovle this, map the boot flash as write-through cache via tlb. And set tlb to remap the flash after code executing in ddr, to confirm flash erase operation properly done. Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-09 20:48:37 +0000