| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
|
|
|
|
|
| |
I can't find anywhere in the datasheet that says the status register needs
3 dummy bytes sent to it before being able to read back the first real
result. Tests on a Blackfin board show that after writing the opcode, the
status register starts coming back immediately. So only write out the
read status register opcode before polling the result.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Since timeouts are only hit when there is a problem in the system, we
don't want to prematurely timeout on a functioning setup. Thus having
low timeouts (in milliseconds) doesn't gain us anything in the production
case, but rather increases likely hood of causing problems where none
otherwise exist.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
|
|
|
|
| |
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some SPI flash drivers like to have extended id information available
(like the spansion flash), so rather than making it re-issue the ID cmd
to get at the last 2 bytes, have the common code read 5 bytes rather than
just 3. This also matches the Linux behavior where it always reads 5 id
bytes from all flashes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Mingkai Hu <Mingkai.hu@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
The common SPI flash code reads the idcode and passes it down to the SPI
flash driver, so there is no need to read it again ourselves.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
|
|
|
|
|
| |
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
|
|
|
|
| |
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
- AT45DB321D
- AT45DB161D
- AT45DB081D
- AT45DB041D
- AT45DB021D
- AT45DB011D
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
| |
Add MTD SPI Flash support for S25FL008A, S25FL016A,
S25FL032A, S25FL064A, S25FL128P.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| | |
Fix NAND support broken during new NAND code merge. Move those few lines of
code to board/netstar/netstar.c
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| | |
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| |
| |
| |
| | |
Divisor field is called PTV not PVT.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_CLPS7111_SERIAL to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_LPC2292_SERIAL to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_KS8695_SERIAL to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_USB_S3C64XX to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_NETARM_SERIAL to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
add CONFIG_SA1100_SERIAL to activate the driver
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| | |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
| |
| |
| |
| |
| | |
Add RTC support.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| | |
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| |
| |
| | |
Make crc32 function to match its prototype. Use more meaningful identifiers.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| | |
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The mpc8313erdb board currently sets DBAT6 to cover all of the final 256MiB of
address space; however, not all of this space is covered by a device. In
particular, flash sits at 0xfe000000-0xfe7fffff, and nothing is mapped
at the far end of the address space.
In zlib, there is a loop that references p[-1] if p is non-NULL. Under
some circumstances, this leads to the CPU speculatively loading from
0xfffffff8 if p is NULL. This leads to a machine check.
Signed-off-by: Scott Wood <scottwood@freescale.com>
continuation to the remaining mpc83xx boards that suffer from the same problem.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch fix the compiler/linker errors
common/cmd_i2c.c:1252: undefined reference to `i2c_get_bus_speed'
common/cmd_i2c.c:1256: undefined reference to `i2c_set_bus_speed'
if board use CONFIG_I2C_CMD_TREE and CONFIG_I2C_MULTI_BUS is not
uesd/undef (wrong define order)
and
removes additional empty lines
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
|
|\ \ \ |
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
We had a bug on 86xx in which the boot page used to bring up secondary
cores was being overwritten and used for the malloc region in u-boot.
We need to reserve the region of memory that the boot page is going to
be put at so nothing uses it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Match determine_mp_bootpg() that was added for 86xx. We need this to
address a bug introduced in v2009.03 with 86xx MP booting. We have to
make sure to reserve the region of memory used for the MP bootpg() so
other u-boot code doesn't use it.
Also added a comment about how cpu_reset() is dealing w/an errata on
early 85xx MP HW.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx
* Introduce determine_mp_bootpg() helper. We'll need this to address a
bug introduced in v2009.03 with 86xx MP booting. We have to make sure
to reserve the region of memory used for the MP bootpg() so other
u-boot code doesn't use it.
* Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to
allow cmd_mp.c to build and work. In the future we should look at
implementing all these functions. This could be common w/85xx if we
use spin tables on 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
We're missing the board_lmb_reserve definitions that allow
cpu_mp_lmb_reserve to be called; this means that Linux
is free to reallocate reserved pages. Linux currently boots
because we're getting lucky - the page we've reserved is
high enough in memory that it isn't allocated by Linux
while we still need it to be in existence.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
For the silicon which doesn't have ROM support in QE, it always needs to load
a pre-built ucode binary to IRAM so that QE can work.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
* Enable backside L2
* e500mc no longer has timebase enable in HID (moved to CCSR register)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
1. wr_lat
UM said the total write latency for DDR2 is equal to
WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
so, the WR_LAT = CL - 1;
2. rd_to_pre
we missed to add the ADD_LAT for DDR2 case.
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
|