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* GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-1653/+1177
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* Update CHANGELOGWolfgang Denk2006-03-25-0/+10
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* Merge with http://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2006-03-24-1028/+18829
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| * Enable Quad UART om MCC200 board.Wolfgang Denk2006-03-23-0/+7
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| * Cleanup MCC200 board configuration; omit non-existent stuff.Wolfgang Denk2006-03-21-22/+5
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| * Update CHANGELOGWolfgang Denk2006-03-19-0/+2
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| * Add support for MPC859/866 Rev. A.0Wolfgang Denk2006-03-18-3/+8
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| * Merge with port of MPC8349EMDS boardWolfgang Denk2006-03-17-40/+2371
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| | * Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-53/+126
| | | | | | | | | | | | multiple-bit errors.
| | * Add command for handling DDR ECC registers on MPC8349EE MDS board.Marian Balakowicz2006-03-16-0/+465
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| | * Fix DDR ECC bit definitions for MPC83xx.Marian Balakowicz2006-03-16-2/+4
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| | * Add initial support for MPC8349E MDS board.Marian Balakowicz2006-03-14-1/+1178
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| | * Add support for ECC DDR initialization on MPC83xx.Marian Balakowicz2006-03-14-22/+110
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| | * Add DMA support for MPC83xx.Marian Balakowicz2006-03-14-1/+173
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| | * Add sync in do_reset() routine for MPC83xx after RPR registerMarian Balakowicz2006-03-14-0/+6
| | | | | | | | | | | | | | | was written to. It is need on some targets when BAT translation is enabled.
| | * Add bit definitions for MPC83xx DDR controller registers.Marian Balakowicz2006-03-14-0/+54
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| | * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-1/+38
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| | * Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+4
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| | * Add support for DS1374 RTC chip.Marian Balakowicz2006-03-14-1/+256
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| * | Add support for Lite5200B board.Wolfgang Denk2006-03-17-83/+192
| |/ | | | | | | Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
| * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer andWolfgang Denk2006-03-13-171/+540
| | | | | | | | | | cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006
| * Fix CHANGELOG entry (patch date)Wolfgang Denk2006-03-13-1/+1
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| * Change max size of uncompressed uImage's to 8MByte and addStefan Roese2006-03-13-3/+23
| | | | | | | | | | | | | | | | | | | | | | CFG_BOOTM_LEN to adjust this setting. As mentioned by Robin Getz on 2005-05-24 the size of uncompressed uImages was restricted to 4MBytes. This default size is now increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN in the board config file. Patch by Stefan Roese, 13 Mar 2006
| * Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.cStefan Roese2006-03-13-1/+4
| | | | | | | | Patch by Stefan Roese, 13 Mar 2006
| * cpu/ppc4xx/start.S : exceptions are enabled after relocationStefan Roese2006-03-13-23/+21
| | | | | | | | Patch by Cedric Vincent, 6 June 2005
| * au1x00_eth.c: check malloc return value and abort if it failedWolfgang Denk2006-03-13-2/+9
| | | | | | | | Patch by Andrew Dyer, 26 Jul 2005
| * Change the sequence of events in soft_i2c.c:send_ack() to keep fromWolfgang Denk2006-03-13-4/+5
| | | | | | | | | | incorrectly generating start/stop conditions on the bus. Patch by Andrew Dyer, 26 Jul 2005
| * Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+7
| | | | | | | | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
| * Fix array overflow with fw_setenv on uninitialised environmentWolfgang Denk2006-03-12-4/+5
| | | | | | | | Patch by Murray Jensen, 15 Jul 2005
| * Add support for EmbeddedPlanet EP88x boardsWolfgang Denk2006-03-12-10/+549
| | | | | | | | Patch by Yuli Barcohen, 13 Jul 2005
| * Remove board specific configuration includes from the common xilinxWolfgang Denk2006-03-12-2/+4
| | | | | | | | | | ethernet and iic adapter code. Patch by Michael Libeskind, 12 Jul 2005
| * Add Nat Semi DP83865 PHY support to MPC85xx TSEC driverWolfgang Denk2006-03-12-0/+64
| | | | | | | | Patch by Murray Jensen, 08 Jul 2005
| * Add (some) definitions for the MPC85xx local bus controllerWolfgang Denk2006-03-12-0/+38
| | | | | | | | Patch by Murray Jensen, 08 Jul 2005
| * Add CPM2 I/O pin functions for MPC85xx processorsWolfgang Denk2006-03-12-0/+149
| | | | | | | | Patch by Murray Jensen, 08 Jul 2005
| * Fix compile problemWolfgang Denk2006-03-12-1/+4
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| * Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc8349adsWolfgang Denk2006-03-12-51/+400
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| | * Added PCI support for MPC8349ADS boardKumar Gala2006-01-12-51/+400
| | | | | | | | | | | | Patch by Kumar Gala 11 Jan 2006
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xxWolfgang Denk2006-03-12-217/+490
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| | * | Enable address translation on MPC83xxKumar Gala2006-02-10-182/+407
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 10 Feb 2006
| | * | Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xxKumar Gala2006-01-25-28/+24
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 25 Jan 2006
| | * | Fixed defines for MPC83xx SICRL register to match current specsKumar Gala2006-01-23-2/+5
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 23 Jan 2006
| | * | Only disable the MPC83xx watchdog if its enabled out of reset.Kumar Gala2006-01-11-0/+10
| | | | | | | | | | | | | | | | | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006
| | * | Allow config of GPIO direction & data registers at boot on 83xxKumar Gala2006-01-11-0/+11
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * | Enable time handling on 83xxKumar Gala2006-01-11-0/+13
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * | Make System IO Config Registers board configurable on MPC83xxKumar Gala2006-01-11-2/+17
| | |/ | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pciWolfgang Denk2006-03-12-11/+86
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| | * | Fixed PCI indirect config ops to handle multiple PCI controllersKumar Gala2006-01-12-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | We need to adjust the bus number we are trying to access based on which PCI controller its on Patch by Kumar Gala 12 Jan 2006
| | * | Report back PCI bus when doing table based device configKumar Gala2006-01-11-0/+4
| | | | | | | | | | | | | | | | Patch by Kumar Gala 11 Jan 2006
| | * | Added support for PCI prefetchable region and BARsKumar Gala2006-01-11-11/+61
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#ft_infrWolfgang Denk2006-03-12-18/+135
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