summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* spi: ti_qspi: Add delay before xfer for am43xxSourav Poddar2014-02-18-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: ti_qspi: Add AM43xx specifics changesSourav Poddar2014-02-18-3/+23
| | | | | | | Add AM43xx specific changes. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* am437x_epos_evm: add SPL API, QSPI, and serial flash supportSourav Poddar2014-02-18-0/+31
| | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* am43xx: Add qspi supportSourav Poddar2014-02-18-1/+5
| | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controllerMarkus Niebel2014-02-18-1/+1
| | | | | | | | The dual lite and solo variant have only 4 SPI controller. respect this in the MXC_SPI_BASE_ADRESSES macro Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3Markus Niebel2014-02-18-2/+7
| | | | | | | | | | SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: spi-mxc: add defines for clk inactive state for ECSPIMarkus Niebel2014-02-18-6/+8
| | | | | | | | | Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: xilinx: Move timeout calculation out of the loopMichal Simek2014-02-18-3/+5
| | | | | | | | Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* serial/serial_arc - add driver for ARC UARTAlexey Brodkin2014-02-07-0/+108
| | | | | | | | | | | | | Driver for non-standard on-chip UART, instantiated in the ARC (Synopsys) FPGA Boards such as ARCAngel4/ML50x Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* x600: Switch to CONFIG_PHYLIBTom Rini2014-02-07-2/+1
| | | | | | | | Now that the designware ethernet driver uses phylib we need to turn it on here. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* net/designware: make driver compatible with data cacheAlexey Brodkin2014-02-07-3/+50
| | | | | | | | | | | | | | | | | | | | Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware - switch driver to phylib usageAlexey Brodkin2014-02-07-379/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net: execute "miiphy_init" if CONFIG_PHYLIB definedAlexey Brodkin2014-02-07-1/+1
| | | | | | | | | | | | | | | | | | | | In "common/Makefile" "miiphyutil.o" gets built if any of the following items enabled: * CONFIG_PHYLIB * CONFIG_MII * CONFIG_CMD_MII So it's possible to not define CONFIG_MII or CONFIG_CMD_MII and still use functions like "miiphy_get_dev_by_name". In its turn "miiphy_get_dev_by_name" traverses "mii_devs" list which is not initialized because "miiphy_init" never got called. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Simon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: add explicit reset of {tx|rx}_currdescnumAlexey Brodkin2014-02-07-0/+2
| | | | | | | | | | | | | | | | | | Driver "init" function might be called multiple times. On every "init" Tx/Rx buffer descriptors are initialized: "descs_init" -> "{tx|rx}_descs_init". In its turn those init functions set MAC's "{tx|rx}desclistaddr" to point on the first buffer descriptor in the list. So CPU to start operation from the first buffer descriptor as well after every "init" we have to reset "{tx|rx}_currdescnum". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: add README for architectureAlexey Brodkin2014-02-07-0/+27
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add architecture to MAKEALLAlexey Brodkin2014-02-07-0/+6
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add AXS101 board supportAlexey Brodkin2014-02-07-0/+460
| | | | | | | | | | | | | | | | | AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add Arcangel4 board supportAlexey Brodkin2014-02-07-0/+196
| | | | | | | | | | | | | | | | Arcangel4 is a FPGA-based development board that is used for prototyping and verificationof of both ARC hardware (CPUs) and software running upon CPU. This board avaialble in 2 flavours: * Little-endian (arcangel4) * Big-endian (arcangel4-be) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add support for standalone programsAlexey Brodkin2014-02-07-0/+13
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: bdinfo, image and arc-specific init functions declarations supportAlexey Brodkin2014-02-07-0/+23
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add library functionsAlexey Brodkin2014-02-07-0/+846
| | | | | | | | | | | These are library functions used by ARC700 architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add cpu filesAlexey Brodkin2014-02-07-0/+734
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add architecture header filesAlexey Brodkin2014-02-07-0/+593
| | | | | | | | | | | | | | | | These are header files used by ARC700 architecture. Also note that "arch-arc700/hardware.h" is only required for compilation of "designware_i2c" driver which refers to "asm/arch/hardware.h". It would be good to fix mentioned driver sometime soon but it will cause changes in ARM board configs that use "designware_i2c". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* blackfin: Initialize the EMAC VLAN with proper default valueAaron Wu2014-02-07-0/+5
| | | | | | | | EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot. Signed-off-by: Aaron Wu <Aaron.Wu@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: Change SMC dcplb entry flag to cover 16M address regionSonic Zhang2014-02-07-1/+2
| | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: init bss earlyBob Liu2014-02-07-1/+1
| | | | | Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: The logic of the BF609 macro is opposite.Sonic Zhang2014-02-07-3/+3
| | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* include/usb/s3c_udc.h: Add <asm/sizes.h>Tom Rini2014-02-06-0/+1
| | | | | | | With e0059ea switching to using SZ_1K, we need to #include <asm/sizes.h> here for everyone to build still. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-06-0/+19
|\
| * fpga: zynqpl: Add support for zc7015 deviceMichal Simek2014-02-06-0/+9
| | | | | | | | | | | | Just extend tables with this new device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: zynq: Correct fpga load when buf is not alignedNovasys Ingenierie2014-02-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | usb: mv_udc: Rename to ci_udcMarek Vasut2014-02-06-111/+111
| | | | | | | | | | | | | | | | | | | | The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
* | usb:gadget:f_thor: cosmetic: Remove debug memsetLukasz Majewski2014-02-06-2/+0
| | | | | | | | | | | | | | | | Apparently debug memset (with a 0x55 value) has been overlooked in the f_thor code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:f_thor: Allocate request up to THOR_PACKET_SIZE not ep->maxpacketLukasz Majewski2014-02-06-1/+1
| | | | | | | | | | | | | | | | Now it is possible to allocate static request - which receives data from the host (OUT transaction) to the size of THOR packet. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driverLukasz Majewski2014-02-06-44/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Allow burst transfers for non EP0 endpintsLukasz Majewski2014-02-06-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removed obscure restriction on the HW setting of DMA transfers. Before this change each transaction sent up to 512 bytes (with packet count equal to 1) for non EP0 transfer. Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 20.74 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Remove redundant cache operation from Samsung UDC driverLukasz Majewski2014-02-06-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A set of cache operations (both invalidation and flush) were redundant in the S3C HS OTG Samsung driver: 1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush the cache (since it is the zero length transmission) 2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not needed when the buffer for OUT EP0 transmission is setup, since no data has yet arrived. Cache cleanups presented above don't contribute much to transmission speed up, hence shall be regarded as cosmetic changes. 3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated. This call is not needed anymore since we reuse the buffers passed from gadgets. This is a key contribution to transmission speed improvement. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurements: Base values (without improvement): Transmission speed: 9.51 MiB/s After the change: Transmission speed: 10.15 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:ums: Replace malloc calls with memalign to fix cache buffer alignmentLukasz Majewski2014-02-06-2/+2
|/ | | | | | | | Calls to malloc() have been replaced by memalign. It now provides proper buffer alignment. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* config: Fix line lengths in include/config_distro_defaults.hTom Rini2014-02-05-2/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* config: add config_distro_defaults.hDennis Gilmore2014-02-04-0/+55
| | | | | | | | describe a set of default features that distros can rely on being available. having this common definition means that distros can easily support systems implementing them. Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* cmd_pxe.c add any option for filesystem with sysboot uses generic loadDennis Gilmore2014-02-04-3/+19
| | | | Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Merge branch 'serial' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-1/+13
|\
| * serial: uartlite: Reset RX/TX in initMichal Simek2014-02-04-1/+13
| | | | | | | | | | | | Just to be sure that there is no pending data. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'net' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+9
|\ \
| * | net: axi_emac: Check if phy was correctly detectedMichal Simek2014-02-04-0/+4
| | | | | | | | | | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: gem: Check if phy was correctly detectedMichal Simek2014-01-21-0/+5
| |/ | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-3/+231
|\ \
| * | microblaze: Add SPL supportMichal Simek2014-02-04-2/+219
| | | | | | | | | | | | | | | | | | | | | Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Enable buffer write for NOR flashesMichal Simek2014-02-04-1/+2
| | | | | | | | | | | | | | | | | | It speeds up writing a lot. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Report priviledged or stack protection exceptionMichal Simek2014-02-04-0/+3
| | | | | | | | | | | | | | | | | | Just list one more exception. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-11-06 14:34:43 +0000