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* imx: ventana: add video enable gpio pinmux for GW54xxTim Harvey2014-08-20-0/+2
| | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: add appropriate delay following GSC i2c writeTim Harvey2014-08-20-1/+1
| | | | | | | The Gateworks System Controller EEPROM config is flash based. Add a delay following writes to avoid errors on back-to-back writes. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: remove caam disable per eeprom bitTim Harvey2014-08-20-1/+1
| | | | | | | During manufacturing this bit is not getting enabled when it should be, so we will ignore it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: set dynamic env var for flash layoutTim Harvey2014-08-20-0/+4
| | | | | | | | | | | NAND devices have differing layouts with respect to page size and pages per block. These parameters affect the parameters that need to be passed to mkfs.ubifs and ubinize used to create UBI images. The various NAND chips supported by Gateworks Ventana fall into two different layouts which we refer to as 'normal' and 'large'. This layout is useful when referencing ubi files to download and flash so we create a dynamic env variable for it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* mx6sxsabresd: Update DDR initializationFabio Estevam2014-08-20-31/+58
| | | | | | | | Use the latest DDR initialization values suggested by the FSL hardware team. While at it, add some comments for clarification. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* pci: mx6: fix occasional link failuresTim Harvey2014-08-20-4/+4
| | | | | | | | | | | | | According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: mx6: Enable Thumb build for SPLMarek Vasut2014-08-20-0/+1
| | | | | | | | | Building the SPL in Thumb mode saves roughly 30% in size of the resulting SPL binary. As the size of SPL it limited on the MX6, this helps a lot. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* ARM: mx6: Handle the MMDCx_MDCTL COL field capricesMarek Vasut2014-08-20-1/+7
| | | | | | | | | The COL field value cannot be easily calculated from the desired column number. Instead, there are special cases for that, see the datasheet, MMDCx_MDCTL field description, field COL . Cater for those special cases. Signed-off-by: Marek Vasut <marex@denx.de>
* ARM: mx6: Prevent overflow in DRAM size detectionMarek Vasut2014-08-20-0/+5
| | | | | | | | | | | | | The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* ARM: mx5: Fix CHSCCDR nameMarek Vasut2014-08-20-1/+1
| | | | | | Fix the name of the CCM CHSCCDR register. Signed-off-by: Marek Vasut <marex@denx.de>
* mx31pdk: Change maintainerFabio Estevam2014-08-20-1/+1
| | | | | | | | | | | Currently I don't have access to a mx31pdk board. Magnus was the original maintainer of the board and accepted to take back this role. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Magnus Lilja <lilja.magnus@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: add support of multi-processor commandGabriel Huau2014-08-20-4/+114
| | | | | | | | | This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* embest/mx6boards: only toggle eMMC usdhc3 RST line on MarSboardIain Paton2014-08-13-0/+1
| | | | | | | | | On MarS usdhc3 is eMMC, on RIoT usdhc3 is uSD and eMMC is usdhc4. Don't run the MarS specific eMMC reset code on usdhc3 when board_type == BOARD_IS_RIOTBOARD Signed-off-by: Iain Paton <ipaton0@gmail.com>
* Update aristainetos board to KconfigStefano Babic2014-08-13-0/+32
| | | | | | | | | | aristainetos board was merged in u-boot-imx before Kconfig was integrated, but it is not yet mainline. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-11-2924/+50912
|\ | | | | | | | | | | | | Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-09-13/+982
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| | * sun7i: Add bananapi boardHans de Goede2014-07-31-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Banana Pi is an A20 based development board using Raspberry Pi compatible IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi and stereo audio out + various expansion headers: http://www.lemaker.org/ Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: HYP/non-sec: configure CNTFRQ on all CPUsMarc Zyngier2014-07-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CNTFRQ needs to be properly configured on all CPUs. Otherwise, virtual machines hoping to find valuable information on secondary CPUs will be disapointed... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: HYP/non-sec: add sun7i PSCI backendMarc Zyngier2014-07-31-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: Add support for a number of new sun7i boardsHans de Goede2014-07-31-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun5i: Add support for a number of new sun5i boardsHans de Goede2014-07-31-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun4i: Add support for a number of new sun4i boardsHans de Goede2014-07-31-2/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: Add CONFIG_MACPWR optionHans de Goede2014-07-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | On some boards the ethernet-phy needs to be powered up through a gpio, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: Enable EHCI on various sunxi boardsHans de Goede2014-07-31-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Most sunxi boards have the EHCI controller hooked up, enable it on all relevant boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun5i: add USB EHCI settingsHans de Goede2014-07-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun5i if CONFIG_USB_EHCI is enabled. Note we don't specify default VBUS gpio pins for sun5i since they vary too much from board to board. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sun4i: add USB EHCI settingsHans de Goede2014-07-31-0/+12
| | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun4i if CONFIG_USB_EHCI is enabled. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * cubieboard2: Enable AXP209 power controllerIan Campbell2014-07-31-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: cubietruck: enable USB EHCIRoman Byshko2014-07-31-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cubietruck has two USB host controllers. This makes them usable by enabling the EHCI driver for them. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Also enable ehci for Cubietruck_FEL] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: add USB EHCI settingsRoman Byshko2014-07-31-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specific USB EHCI settings to be set for sun7i if CONFIG_USB_EHCI is enabled. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Use SUNXI_GPH macro for SUNXI_USB_VBUS#_GPIO] [hdegoede@redhat.com: Add #ifndef SUNXI_USB_VBUS#_GPIO to allow override of the default pins from boards.cfg] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add general USB settingsRoman Byshko2014-07-31-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General configuration settings to be set if CONFIG_USB_EHCI is enabled for an Allwinner aka sunxi SoC. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add USB EHCI driverRoman Byshko2014-07-31-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: add defines to control USB Host clocks/resetsRoman Byshko2014-07-31-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit adds three defines which will be used in the EHCI driver to enable USB clock and assert reset controllers of the corresponding PHYs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-31-9/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | Prepare v2014.10-rc1Tom Rini2014-08-06-2/+2
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | Change Andy Fleming's email addressAndy Fleming2014-08-06-5/+5
| | | | | | | | | | | | | | | | | | | | | Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com>
| * | The _config target is not present anymore, mention _defconfig insteadHolger Freyther2014-08-06-11/+11
| | | | | | | | | | | | | | | The _config part is gone for sure, the _defconfig target could at least work. I have not verified this for all targets though.
| * | git-mailrc: add a kconfig aliasStephen Warren2014-08-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc alias. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | doc: README.SPL: adjust for Kbuild and KconfigMasahiro Yamada2014-08-06-22/+6
| | | | | | | | | | | | | | | | | | Reflect the latest build system to doc/README.SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | doc: delete README.ARM-SoCMasahiro Yamada2014-08-06-31/+0
| | | | | | | | | | | | | | | | | | This document is too old and useless. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-08-06-8/+31
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| | * | spi, spi_mxc: do not hang in spi_xchg_singleHeiko Schocher2014-08-06-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | spi: Support half-duplex mode in FDT decodeSimon Glass2014-08-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This parameter should also be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | exynos: spi: Fix calculation of SPI transaction start timeSimon Glass2014-08-06-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | cros_ec: Fix two bugs in the SPI implementationSimon Glass2014-08-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An incorrect message version is passed to the EC in some cases and the parameters of one function are switched. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | sf: sf_ops: Stop leaking memoryMarek Vasut2014-08-06-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | It's usually a common pattern to free() the memory that we allocated. Implement this here to stop leaking memory. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+83
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| | * | kmp204x: prepare to use CPU watchdogBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch configures the qrio to trigger a core reset on a CPU reset request. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x/qrio: support for setting the CPU reset request modeBoschung, Rainer2014-08-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN flag in the qrio RESCNF reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x: set CPU watchdog reset reason flagBoschung, Rainer2014-08-01-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | kmp204x/qrio: prepare support for the CPU watchdog reset reasonBoschung, Rainer2014-08-01-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog flag in the REASON1 reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-06 14:45:44 +0000