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* bios_emulator: Add an option to enable debuggingSimon Glass2014-11-25-54/+90
| | | | | | | | | | At present there are DEBUG options spread around the place. If you enable one and not another you can end up with an emulator that does not work, since each file can have a different view of what the registers look like. To fix this, create a global CONFIG_X86EMU_DEBUG option that keeps everything consistent. Signed-off-by: Simon Glass <sjg@chromium.org>
* bios_emulator: Allow a custom interrupt handler to be installedSimon Glass2014-11-25-0/+6
| | | | | | | Sometime we want to provide an interrupt handler for the ROM, Add a function to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
* bios_emulator: Add vesa support and allow ROMs to be passed in as dataSimon Glass2014-11-25-58/+152
| | | | | | | | | As well as locating the ROM on the PCI bus, allow the ROM to be supplied to the emulator. Split the init up a little so that callers can supply their own interrupt routines. Also allow a vesa mode to be provided, to be selected once the BIOS run is complete. Signed-off-by: Simon Glass <sjg@chromium.org>
* bios_emulator: Allow x86 to use the emulatorSimon Glass2014-11-25-23/+23
| | | | | | | | | | | There is an implicit assumption that x86 machines want to use raw I/O in the BIOS emulator, but this should be selectable. Add an CONFIG_X86EMU_RAW_IO option to control it instead. Also fix a few bugs which cause warnings on x86 and adjust the Makefile to remove the assumption that only PowerPC uses the emulator. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable video support for chromebook_linkSimon Glass2014-11-25-7/+3
| | | | | | | Now that we have the required drivers, enable video support with a suitable option ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
| | | | | | This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+969
| | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow an option ROM to be built into U-BootSimon Glass2014-11-25-0/+3
| | | | | | | | Some x86 machines require a binary blob containing 16-bit initialisation code for their video hardware. Allow this to be built into the x86 ROM so that it is accessible during boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: video: Add video driver for bare x86 boardsSimon Glass2014-11-25-0/+38
| | | | | | | | Add a very simple driver which uses vesa to discover the video mode and then provides a frame buffer for use by U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* pci: Add general support for execution of video ROMsSimon Glass2014-11-25-2/+353
| | | | | | | | | | | | | | | | | | Some platforms don't have native code for dealing with their video hardware. In some cases they use a binary blob to set it up and perform required actions like setting the video mode. This approach is a hangover from the old PC days where a ROM was provided and executed during startup. Even now, these ROMs are supplied as a way to set up video. It avoids the code for every video chip needing to be provided in the boot loader. But it makes the video much less flexible - e.g. it is not possible to do anything else while the video init is happening (including waiting hundreds of milliseconds for display panels to start up). In any case, to deal with this sad state of affairs, provide an API for execution of x86 video ROMs, either natively or through emulation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
| | | | | | | | On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add support for Vesa BIOS extensionsSimon Glass2014-11-25-0/+103
| | | | | | | For option ROMs we can use these extensions to request a particular video mode. Add a header file which defines the binary interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
| | | | | | Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
| | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
* Introduce a header file for the BIOS emulatorSimon Glass2014-11-25-52/+46
| | | | | | | We should have a public header so that users can avoid defining functions themselves. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a definition of asmlinkageSimon Glass2014-11-25-0/+3
| | | | | | | This is needed to permit calling C from assembler without too much pain. Add a definition for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable SPI for chromebook_linkSimon Glass2014-11-25-4/+0
| | | | | | Enable SPI so that the SPI flash can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
| | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
| | | | | | These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+528
| | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
| | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
| | | | | | | This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unnecessary call to initr_enable_interrupts()Bin Meng2014-11-25-1/+1
| | | | | | | | | Actually initr_enable_interrupts() was never called in an x86 build due to it was wrapped by CONFIG_x86 (typo of X86). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
| | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-9/+1
| | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
| | | | | | | | | | | | | Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
| | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
| | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable USB on linkSimon Glass2014-11-25-2/+0
| | | | | | Enable USB support on link - there are two EHCI ports available. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
| | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-1/+7
| | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+334
| | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
| | | | | | Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
| | | | | | | | These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-4/+572
| | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
| | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
| | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+167
| | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+49
| | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add functions to read and write a BAR addressSimon Glass2014-11-25-3/+44
| | | | | | | | | Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: config: Enable plug-and-play for link PCISimon Glass2014-11-25-0/+3
| | | | | | | | Enable this option so that we can configure the available PCI devices. Also make sure that PCI is available early after relocation as we use it for several other subsystems. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+15
| | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
| | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
* rtc: mc146818: Set up RTC at start of daySimon Glass2014-11-25-5/+45
| | | | | | | Provide a function to set up the RTC ready for use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
| | | | | | | | | Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
| | | | | | | | | Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Panic if there is no relocation dataSimon Glass2014-11-25-0/+3
| | | | | | | | | This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove board_early_init_r()Simon Glass2014-11-25-20/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Update pci_ids.h to include some missing IDsSimon Glass2014-11-25-6/+181
| | | | | | | This was taken from Linux 3.18 with some additional IDs from Chrome OS Coreboot commit 688ef385. Signed-off-by: Simon Glass <sjg@chromium.org>
* Align embedded device tree correctlySimon Glass2014-11-25-0/+2
| | | | | | | | Device trees must be aligned to a 4-byte boundary. This was dropped in the Kbuild conversion. Bring it back, and use 16-byte alignment for good measure. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 20:25:20 +0000