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* configs: omap5_common : Boot rootfs from sd card by defaultFranklin S Cooper Jr2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | * Since the emmc isn't always programed trying to load the fs from the emmc causes boot failures/kernel panic. * The current bootcmd is set to: bootcmd=run findfdt; run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; \ setenv mmcroot /dev/mmcblk0p2 rw; run mmcboot; My guess is the env variables should be set so that sd card boot (dt,kernel,fs) is the default and then fallback to emmc if it fails (no sd card detected) The current bootcmd attempts to set mmcroot to the sd card rootfs but that code doesn't run due to mmcboot being ran early on. Signed-off-by: Franklin Cooper Jr. <fcooper@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap-common: emif: allow to map memory without interleavingFelipe Balbi2014-12-04-4/+5
| | | | | | | | | If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* usb: phy: omap_usb_phy: fix build breakageFelipe Balbi2014-12-04-2/+0
| | | | | | | | | | there's no such function usb3_phy_power(), it's likely that author meant to call, usb_phy_power() instead, but that's already called properly from xhci-omap.c. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: prcm: add missing registersFelipe Balbi2014-12-04-0/+3
| | | | | | | | | some boards might want to use USB1 for host, without fiddling those registers it'll be impossible. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-04-10/+10
| | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: don't enable misc_init_r by defaultFelipe Balbi2014-12-04-14/+1
| | | | | | | | | | Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* Revert "image-fdt: boot_get_fdt() return value when no DTB exists"Tom Rini2014-12-03-2/+2
| | | | | | | | | | | | | It has been found that this change breaks the case of an appended device tree file, so for the problem in question some other solution must be found. This reverts commit c6150aaf2f2745141a7c2ceded58d7efbfeace7d. Reported-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Reported-by: Pantelis Antoniou <panto@antoniou-consulting.com> Confirmed-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Tom Rini <trini@ti.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2014-12-01-33/+7
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| * fdt: Fix regression in fdt_pack_reg()Hans de Goede2014-12-01-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 933cdbb479: "fdt: Try to use fdt_address_cells()/fdt_size_cells()" I noticed that allwinner boards would no longer boot. Switching to fdt_address_cells / fdt_size_cells changes the result from bytes to 32 bit words, so when we increment pointers into the blob, we must do so by 32 bit words now. This commit makes allwinner boards boot again. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Vince Hsu <vinceh@nvidia.com>
| * fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada2014-11-27-27/+1
| | | | | | | | | | | | | | | | | | | | The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-01-363/+5872
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| * | tools: Add ifdtool to .gitignoreBin Meng2014-11-25-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: chromebook_link: Enable the Chrome OS ECSimon Glass2014-11-25-0/+9
| | | | | | | | | | | | | | | | | | Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: chromebook_link: Enable the x86 emulatorSimon Glass2014-11-25-0/+4
| | | | | | | | | | | | | | | | | | Enable this so that it can be used instead of native execution if desired. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Always print errors when opcode decode failsSimon Glass2014-11-25-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a rare event and should not happen. When it does it is confusing to work out why. At least we should print a message. Adjust the emulator to always print decode errors to the console. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Add an option to enable debuggingSimon Glass2014-11-25-54/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there are DEBUG options spread around the place. If you enable one and not another you can end up with an emulator that does not work, since each file can have a different view of what the registers look like. To fix this, create a global CONFIG_X86EMU_DEBUG option that keeps everything consistent. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Allow a custom interrupt handler to be installedSimon Glass2014-11-25-0/+6
| | | | | | | | | | | | | | | | | | | | | Sometime we want to provide an interrupt handler for the ROM, Add a function to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Add vesa support and allow ROMs to be passed in as dataSimon Glass2014-11-25-58/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | As well as locating the ROM on the PCI bus, allow the ROM to be supplied to the emulator. Split the init up a little so that callers can supply their own interrupt routines. Also allow a vesa mode to be provided, to be selected once the BIOS run is complete. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Allow x86 to use the emulatorSimon Glass2014-11-25-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an implicit assumption that x86 machines want to use raw I/O in the BIOS emulator, but this should be selectable. Add an CONFIG_X86EMU_RAW_IO option to control it instead. Also fix a few bugs which cause warnings on x86 and adjust the Makefile to remove the assumption that only PowerPC uses the emulator. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable video support for chromebook_linkSimon Glass2014-11-25-7/+3
| | | | | | | | | | | | | | | | | | | | | Now that we have the required drivers, enable video support with a suitable option ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
| | | | | | | | | | | | | | | | | | This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+969
| | | | | | | | | | | | | | | | | | | | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Allow an option ROM to be built into U-BootSimon Glass2014-11-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Some x86 machines require a binary blob containing 16-bit initialisation code for their video hardware. Allow this to be built into the x86 ROM so that it is accessible during boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: video: Add video driver for bare x86 boardsSimon Glass2014-11-25-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Add a very simple driver which uses vesa to discover the video mode and then provides a frame buffer for use by U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | pci: Add general support for execution of video ROMsSimon Glass2014-11-25-2/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms don't have native code for dealing with their video hardware. In some cases they use a binary blob to set it up and perform required actions like setting the video mode. This approach is a hangover from the old PC days where a ROM was provided and executed during startup. Even now, these ROMs are supplied as a way to set up video. It avoids the code for every video chip needing to be provided in the boot loader. But it makes the video much less flexible - e.g. it is not possible to do anything else while the video init is happening (including waiting hundreds of milliseconds for display panels to start up). In any case, to deal with this sad state of affairs, provide an API for execution of x86 video ROMs, either natively or through emulation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
| | | | | | | | | | | | | | | | | | | | | | | | On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Add support for Vesa BIOS extensionsSimon Glass2014-11-25-0/+103
| | | | | | | | | | | | | | | | | | | | | For option ROMs we can use these extensions to request a particular video mode. Add a header file which defines the binary interface. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
| | | | | | | | | | | | | | | | | | Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
| | | | | | | | | | | | | | | | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Introduce a header file for the BIOS emulatorSimon Glass2014-11-25-52/+46
| | | | | | | | | | | | | | | | | | | | | We should have a public header so that users can avoid defining functions themselves. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a definition of asmlinkageSimon Glass2014-11-25-0/+3
| | | | | | | | | | | | | | | | | | | | | This is needed to permit calling C from assembler without too much pain. Add a definition for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable SPI for chromebook_linkSimon Glass2014-11-25-4/+0
| | | | | | | | | | | | | | | | | | Enable SPI so that the SPI flash can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
| | | | | | | | | | | | | | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
| | | | | | | | | | | | | | | | | | These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+528
| | | | | | | | | | | | | | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
| | | | | | | | | | | | | | | | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
| | | | | | | | | | | | | | | | | | | | | This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Remove unnecessary call to initr_enable_interrupts()Bin Meng2014-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Actually initr_enable_interrupts() was never called in an x86 build due to it was wrapped by CONFIG_x86 (typo of X86). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
| | | | | | | | | | | | | | | | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
| | | | | | | | | | | | | | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable USB on linkSimon Glass2014-11-25-2/+0
| | | | | | | | | | | | | | | | | | Enable USB support on link - there are two EHCI ports available. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
| | | | | | | | | | | | | | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add SATA settings for linkSimon Glass2014-11-25-1/+7
| | | | | | | | | | | | | | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+334
| | | | | | | | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
| | | | | | | | | | | | | | | | | | Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-4/+572
| | | | | | | | | | | | | | | | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 15:22:07 +0000