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* OMAP3 MMC: Fix warning dereferencing type-punned pointerDirk Behme2009-10-13-27/+28
| | | | | | | | | Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Steve Sakoman <sakoman@gmail.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* Support for the OpenRD base boardSimon Kagstrom2009-10-13-0/+691
| | | | | | | The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Kirkwood: mv88f6281gtw_ge: Add kwbimage build supportPrafulla Wadaskar2009-10-13-0/+168
| | | | | | | | | | | This patch adds kwbimage configuration file (used by mkimage utility) to support u-boot.kwb target on mv88f6281gtw_ge board. To create Kirkwood boot image to be flashed on SPI Flash, additional parameter u-boot.kwb need to be passed during make. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Kirkwood: rd6281a: Add kwbimage build supportPrafulla Wadaskar2009-10-13-0/+170
| | | | | | | | | | | This patch adds kwbimage configuration file (used by mkimage utility) to support u-boot.kwb target on rd6281a platform. To create Kirkwood boot image to be flashed on NAND, additional parameter u-boot.kwb need to be passed during make. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-1/+900
| | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-3/+702
| | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* TI: DaVinci DM365: Minor config cleanupSandeep Paulraj2009-10-13-2/+0
| | | | | | | | | | The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag. This is already included when we include the config_cmd_default.h header file. So this flag is removed. Also another flag to enable NAND functions was being enabled incorrectly. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci DM365: Removing header file which does not existSandeep Paulraj2009-10-13-1/+0
| | | | | | | The DaVinci DM365 EVM board specific code was including a header file which does not exist. So removing this header file. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM355: Config Cleanup and UpdateSandeep Paulraj2009-10-13-9/+12
| | | | | | | | | | | | | | | | | | This patch does the following 1) Enables the NAND driver which is now available. 2) Enables the 'CONFIG_MTD_DEVICE' as without this the compilation will fail 3) We now have a safe place to store environment and defines an offset where this can be stored. This offset value is such that it is after the location where U-Boot is flashed using TI flash utilities. 4) Enables Bootdelay 5) Increases malloc() arena size. Manufacturers are coming out with NAND with large blocks sizes of upto 1 MiB. It has been noticed that as the block size of the NAND used is increased, if this particular value is not increased, the NAND driver will output out of memory errors. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM646x: Initial Support for DM646x SOCSandeep Paulraj2009-10-13-0/+53
| | | | | | | | | DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM6446: Fix Compilation error in NAND modeSandeep Paulraj2009-10-13-0/+1
| | | | | | | | | | | | The Default mode that is built for the Davinci DVEVM happens to be the NOR mode. When we want to build for the NAND mode, we get a compilation error. This is overcome by defining the CONFIG_MTD_DEVICE flag in the NAND mode. The image built for NAND mode was successfully tested on the DaVinci DM6446 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3 Move cache routine to cache.STom Rix2009-10-13-184/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* TI DaVinci: Remove references to SZ_xxSandeep Paulraj2009-10-13-19/+13
| | | | | | | | | | This patch removes the asm/sizes.h header file from being included in the DaVinci SOC configs. References to SZ_xx have been replaced by appropriate bit shifted values. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-10-12-106/+460
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| * Update all board to support new bbmiiphy driver (with multibus support)Luigi 'Comio' Mantellini2009-10-10-0/+74
| | | | | | | | | | Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Add bb_miiphy_init call before any ethernet bring-up code.Luigi 'Comio' Mantellini2009-10-10-1/+64
| | | | | | | | | | Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an ↵Luigi 'Comio' Mantellini2009-10-10-105/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arbitrary number of mii buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define at least the following macros: MII_INIT - Generic code to enable the MII bus (optional) MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin (optional) MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill the bb_miiphy_buses[] array with a record for each required bus and declare the bb_miiphy_buses_num variable with the number of mii buses. The record (struct bb_miiphy_bus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Leave x86emu op code tables in default sectionEd Swarthout2009-10-12-14/+8
|/ | | | | | | | Forcing the tables into got2 caused extra relocation when using -mrelocatable. This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Jin Zhengxiong <Jason.Jin@freescale.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-1413/+154
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| * relocation: Do not relocate NULL pointers.Joakim Tjernlund2009-10-08-24/+48
| | | | | | | | | | | | | | | | | | | | NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * 85xx: Ensure BSS segment isn't linked at address 0Peter Tyser2009-10-08-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is relocated from flash to RAM pointers are modified accordingly. However, pointers initialzed with NULL values should not be modified so that they maintain their intended NULL value. If the BSS segment is linked at address 0 its address will not be updated as necessary during relocation. This is a temporary workaround. The end goal is to add support to U-Boot to dynamically locate the BSS at an arbitrary address at runtime. When the ability to fixup the BSS inteligently is added, this workaround can be removed and the 85xx link script can put the BSS at a fixed address at link time. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove reloc_off field from global_data structurePeter Tyser2009-10-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that proper relocation is supported, the reloc_off field is no longer necessary. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We therefore increment XF_VERSION to 6 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * arm/microblaze/nios/nios2/sh: Remove relocation fixupsPeter Tyser2009-10-03-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These architectures don't need relocation fixups, so reduce their codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS. Also remove the reloc_off field from their global data structures as it is no longer needed. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We will therefore increment XF_VERSION in the next commit, which also touches this area. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Conditionally perform common relocation fixupsPeter Tyser2009-10-03-5/+41
| | | | | | | | | | | | | | | | | | | | | | Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * p3mx: Remove serial relocation fixupsPeter Tyser2009-10-03-11/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * lwmon, lwmon5: Remove sysmon POST relocation fixupsPeter Tyser2009-10-03-32/+2
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * mpl: Remove memory test relocation fixupsPeter Tyser2009-10-03-33/+1
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * fpga: Remove relocation fixupsPeter Tyser2009-10-03-863/+18
| | | | | | | | | | | | | | | | PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * tsec: Remove PHY command relocation fixupsPeter Tyser2009-10-03-49/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove board-specific command table relocation fixupsPeter Tyser2009-10-03-71/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove extable relocation fixupsPeter Tyser2009-10-03-20/+6
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove pci config table pointer relocation fixupsPeter Tyser2009-10-03-25/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove board.c relocation fixupsPeter Tyser2009-10-03-50/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Check for compilers that don't support relocationPeter Tyser2009-10-03-0/+6
| | | | | | | | | | | | | | | | | | | | Certain ppc compilers are known not to generate the .fixup section properly. The .fixup section is necessary to create a relocatable U-Boot image. A basic check for the existence of the .fixup section should hopefully catch the majority of broken compilers which don't support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-223/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | tqm5200: Correct comment and code in post_hotkeys_pressed.Detlev Zundel2009-10-08-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the code and the comment according to the original intent of doing an intensive memory test when PSC6_3 is pulled low on the STK52xx. Notably PORT_CONFIG will be overridden with this correct code now, so beware. The original code only worked by coincidence depending on the PORT_CONFIG setting from the header file. The new code was tested to ensure that the (undocumented) memory test still works on the STK52x. Signed-off-by: Detlev Zundel <dzu@denx.de> CC: Martin Krause <Martin.Krause@tqs.de> Minor white-space cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-21/+37
| | | | | | | | | | | | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: respect 80-chars per line in ppc*.h filesNiklaus Giger2009-10-07-870/+1038
| | | | | | | | | | | | | | | | After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Rework cmd reginfoNiklaus Giger2009-10-07-154/+378
| | | | | | | | | | | | | | | | | | | | The command "reginfo" got an overhaul for the ppc4xx. It dumps all the relevant HW configuration registers (address, symbolic name, content). This allows to easily detect errors in *.h files and changes in the HW configuration. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-492/+492
| | | | | | | | | | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Cleanup some HW register namesNiklaus Giger2009-10-07-189/+216
| | | | | | | | | | | | | | | | | | | | Here you find all the changes in the include directory for new register names and adapting other ones to the names used by AMCC in their manuals, e.g. For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008 For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006 Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add PPC405EX(r) Rev D supportStefan Roese2009-10-07-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com>
* | ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-1/+17
| | | | | | | | | | | | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | PPC4xx: Denali core: Fix incorrect DDR row bitsMike Nuss2009-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPD detection code for the Denali memory controller used on some ppc4xx processors incorrectly encodes DDR0_42. With certain memory configurations, this can cause the bootwrapper to incorrectly calculate the installed memory size, because the number of row bits is wrong. This patch fixes that encoding. Signed-off-by: Mike Nuss <mike@terascala.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Add information about return values of xxx_eth_register() in documentationBen Warren2009-10-05-8/+13
| | | | | | | | | | | | | | | | | | As discussed on mailing list, <0 indicates failure, >=0 indicates number of interfaces found. Also added blurb about private data Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | document network driver frameworkMike Frysinger2009-10-04-0/+177
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | net: kirkwood_egiga.c: fixed build warningPrafulla Wadaskar2009-10-04-1/+3
| | | | | | | | | | | | | | | | if link up detection code is disabled through config option, it gives build warning. This patch fixes the same Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI APIBen Warren2009-10-04-639/+849
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | net: phy: mv88e61xx.c : fixed build warningPrafulla Wadaskar2009-10-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | following build warning was observed mv88e61xx.c: In function ‘mv88e61xx_busychk’: mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules This patch fixes the same Patch tested for rd6281a board build Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | net: Fix problem with 405EZ ethernet interruptJames Clough2009-10-04-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the UIC. We need to acknowledge the RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. This problem was introduced with commit d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines] Signed-off-by: James Clough <james@rtetc.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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