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* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+163
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add GPIO supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+349
| | | | | | This driver only supports Driver Model, not legacy model. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: i2c: add LPC32xx I2C interface supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+268
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: mtd: nand: add MLC NAND controllerAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+776
| | | | | | | | | | The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add Ethernet supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+659
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* Merge branch 'u-boot/master'Albert ARIBAUD2015-04-10-4289/+5138
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| * ARM: zynq: Remove Jagan from list of maintainersMichal Simek2015-04-08-1/+0
| | | | | | | | | | | | Email address is not longer valid that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: disable CONFIG_SYS_MALLOC_F to fix MMC bootMasahiro Yamada2015-04-08-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 326a682358c1 (malloc_f: enable SYS_MALLOC_F by default if DM is on), Zynq MMC boot hangs up after printing the following: U-Boot SPL 2015.04-rc5-00053-gadcc570 (Apr 08 2015 - 12:59:11) mmc boot reading system.dtb Prior to commit 326a682358c1, Zynq boards enabled CONFIG_DM, but not CONFIG_SYS_MALLOC_F. That commit forcibly turned on CONFIG_SYS_MALLOC_F. I have not figured out the root cause, but anyway it looks like CONFIG_SYS_MALLOC_F gave a bad impact on the Zynq MMC boot. We are planning to have the v2015.04 release in a few days. I know this is a defensive fixup, but what I can do now is to add # CONFIG_SYS_MALLOC_F is not set to every Zynq defconfig file to get back the original behavior. Tested on: - Zedboard - ZC706 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org>
| * cmd_mem.c: Update 'iteration_limit' to unsigned longTom Rini2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | With e37f1eb we now use strict_strtoul() in do_mem_mtest() and this gives us a warning: ../include/vsprintf.h:38:5: note: expected 'long unsigned int *' but argument is of type 'int *' Signed-off-by: Tom Rini <trini@konsulko.com>
| * fix makefiles to respect DTC settingPavel Machek2015-04-07-1/+1
| | | | | | | | | | | | | | Top-level Makefile has option to select dtc binary, but it is ignored due to bug in Makefile.lib. Fix it. Signed-off-by: Pavel Machek <pavel@denx.de>
| * MAKEALL: fix get_target_arch() to adjust to '-' in Status fieldMasahiro Yamada2015-04-07-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Kconfig conversion, boards.cfg scanned by MAKEALL is generated by tools/genboardscfg.py. Every board is supposed to have its own MAINTAINERS that contains maintainer and status information, but, in fact, MAINTAINERS is missing from some boards. For such boards, the first field, Status, is filled with '-'. It causes a problem for "set" command, which ignores '-' in its arguments. Consequently, get_target_arch() returns a wrong field and MAKEALL fails to get a correct toolchain. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * kbuild: include config.mk when auto.conf is not older than .configMasahiro Yamada2015-04-07-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Kconfig conversion, config.mk has been included only when include/config/auto.conf is newer than the .config file. It causes build error if both files have the same time-stamps. It is actually possible because EXT* file systems have a 1s time-stamp resolution. The config.mk should be included when include/config/auto.conf is *not older* than the .config file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Tom Rini <trini@konsulko.com> Reported-by: York Sun <yorksun@freescale.com> Reported-by: Stephen Warren <swarren@nvidia.com> Reported-by: Matthew Gerlach <mgerlach@opensource.altera.com> Tested-by: Stephen Warren <swarren@nvidia.com>
| * am33xx/ddr.c: Fix regression on DDR2 platformsTom Rini2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in fc46bae a "clean up" was introduced that intended to reconcile some of the AM335x codepaths based on how AM43xx operates. Unfortunately this introduced a regression on the DDR2 platforms. This was un-noticed on DDR3 (everything except for Beaglebone White) as we had already populated sdram_config correctly in sequence. This change brings us back to the older behavior and is fine on all platforms. Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * cmd_mem: cleanups, catch bad usagePavel Machek2015-04-07-15/+19
| | | | | | | | | | | | | | Currently, memtest will silently accept bad data. Perform error checking on user intput. Signed-off-by: Pavel Machek <pavel@denx.de>
| * ahci: Fix a wrong parameter passTang Yuantian2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In stead of user_buffer_size, transfer_size should be used to pass to ahci_device_data_io(). transfer_size is the length that we want the low level function to transfer each time. If we use user_buffer_size which is the totally data length as parameter, low level function will actually create many SGs to transfer as many data as possible each time. That will produce many redundant data transfer. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * env_sf: Fix recovery defaultMario Schuknecht2015-04-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot environment is redundantly stored in a NOR flash on our boards. Redundant means that there are two places to store the environment. But only one of the two is active. I discovered that on one board the u-boot (env_sf) uses the environment from the second place and the Kernel (fw_printenv) uses the environment from the first place. To decide which is the active environment there is a byte inside the environment. 1 means active and 0 means obsolete. But on that board both environments had have a 1. This can happen if a power loss or reset occurs during writing the environment. In this situation the u-boot (env_sf) implementation uses the second environment as default. But the Kernel (fw_printenv) implementation uses the first environment as default. This commit corrects the default in the u-boot env_sf implementation when a problem was detected. Now the recovery default is the same like in all other environment implementations. E.g. fw_printenv and env_flash. This ensures that u-boot and Kernel use the same environment. Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-04-06-28/+193
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| | * config: exynos: trats2: Enable support for Image.itb at trats2 deviceŁukasz Majewski2015-04-06-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | After this change it is possible to boot trats2 device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * config: exynos: trats: Enable support for Image.itb at trats deviceŁukasz Majewski2015-04-06-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | After this change it is possible to boot trats device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * config: exynos: common: Provide env variables to support Image.itbŁukasz Majewski2015-04-06-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change allows using Image.itb image format with Exynos4 devices (especially trats and trats2). Such change facilitates automated testing since only one binary needs to be prepared. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * smdk5420: Remove GPIO enumsAjay Kumar2015-04-06-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove GPIOs from smdk5420 board file and because the same is already specified via DT. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * dts: peach_pi: Add DT properties needed for displayAjay Kumar2015-04-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * dts: peach_pit: Add SLP and RST GPIO properties in parade DT nodeAjay Kumar2015-04-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that parade driver supports reading SLP and RST GPIO from DT, specify the same in parade DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD nodeAjay Kumar2015-04-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the exynos_fb driver supports handling backlight GPIO via DT, specify pwm output property via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * video: parade: configure SLP and RST GPIOs if specified in DTAjay Kumar2015-04-06-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure EDP_RST GPIO and EDP_SLP GPIO, if provided in parade DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * video: exynos_fb: configure backlight GPIOs if specified in DTAjay Kumar2015-04-06-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure PWM_OUT(PWM output) GPIO and BL_EN(backlight enable) GPIO, if provided in FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panelsAjay Kumar2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm: exynos: add display clocks for Exynos5800Ajay Kumar2015-04-06-3/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * config: peach: Correct memory layout environment settingsSjoerd Simons2015-04-06-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The peach boards have their SDRAM start address at 0x20000000 instead of 0x40000000 which seems common for all other exynos5 based boards. This means the layout set in exynos5-common.h causes the kernel be loaded more then 128MB (at 0x42000000) away from memory start which breaks booting kernels with CONFIG_AUTO_ZRELADDR Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses the same offsets from start of memory as the common exynos5 settings. This fixes booting via bootz and PXE Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos5: add trace feature #ifdef in exynos5-common.hInha Song2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can enable / disable trace feature from the FTRACE config options. To enable, compile U-Boot with FTRACE=1. This patch add #ifdef FTRACE in exynos5-common.h for enable/disable to use FTRACE configs instead of having to change board config files. Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | sunxi: Fix Orangepi_mini dtb filenameHans de Goede2015-04-04-1/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | The Orangepi_mini is different enough from the regular Orangepi that it needs its own dtb, but when it got added a copy and paste error was made and it got the same dtb filename, fix this. While at it also add a short description of both Orangepi boards to the defconfig files for them. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * Merge git://git.denx.de/u-boot-arcTom Rini2015-04-03-583/+602
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| | * board: AXS10x - update SDIO clock valueAlexey Brodkin2015-04-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the most recent board firmware correct SDIO clock is 50MHz as opposed to 25 MHz before. Also set max frequency of MMC data exchange equal to SDIO clock - because there's no way to transfer data faster than interface clock. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: add support for SLC (System Level Cache, AKA L2-cache)Alexey Brodkin2015-04-03-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * board: Switch Abilis TB-100 board to Driver Model for serial portAlexey Brodkin2015-04-03-5/+31
| | | | | | | | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| | * serial-arc: switch to DMAlexey Brodkin2015-04-03-32/+129
| | | | | | | | | | | | | | | | | | | | | | | | Now when all infrastructure in ARC is ready for it let's switch ARC UART to driver model. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| | * arc: minor fixes in KconfigAlexey Brodkin2015-04-03-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line lenth selection is correctly enabled if either I$ or D$ are enabled. [2] Add dummy entry to target list to make sure target type is always mentioned in defconfig. Otherwise defconfig for the first target in the list will not have target name and later on with addition of the new target on top of the list in Kconfig will lead to corrupted configuration expanded from defconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATAAlexey Brodkin2015-04-03-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed on mailing list we're drifting away from CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem() for global data. So do this for ARC architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: re-generate defconfigsAlexey Brodkin2015-04-03-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before that moment our defconfigs were manually modified with addition of new options. That means once anybody wants to add another option and re-genarate defconfig with "make defconfig" there will be lots of differences. So to make future modifications more clean we'll do bulk re-generation right away. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: clean-up init procedureAlexey Brodkin2015-04-03-81/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intention behind this work was elimination of as much assembly-written code as it is possible. In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc. It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86. Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
| | * arc: move low-level interrupt and exception handlers in a separate fileAlexey Brodkin2015-04-03-144/+152
| | | | | | | | | | | | | | | | | | | | | | | | This separation makes maintenance of code easier because those low-level interrupt- or exception handling routines are pretty static and usually require not much care while start-up code is a subject of modifications and enhancements. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: merge common start-up code between ARC and ARCv2Alexey Brodkin2015-04-03-294/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ARCompact and ARCv2 are not binary compatible most of assembly instructions are used in both. With this change we'll get rid of duplicate code. Still IVTs are implemented differently so we're keeping them in separate files. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: cache - build invalidate_icache_all() and invalidate_dcache_all()Alexey Brodkin2015-04-03-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | always Make both invalidate_icache_all() and invalidate_dcache_all() available even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or CONFIG_SYS_ICACHE_OFF. This is useful because configuration of U-Boot may not match actual hardware features. Real board may have cache(s) but for some reason we may want to run U-Boot with cache(s) disabled (for example if some peripherals work improperly with existing drivers if data cache is enabled). So board may start with cache(s) enabled (that's the case for ARC cores with built-in caches) but early in U-Boot we disable cache(s) and make sure all contents of data cache gets flushed in RAM. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * serial/serial_arc: set registers address during compilationAlexey Brodkin2015-04-03-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Being global variable with 0 value it falls into .bss area which we may only use after relocation to RAM. And right afetr relocation we zero .bss - effectively cleaing register address set for early console. Now with pre-set value "regs" variable is no longer in .bss and this way safely survives relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-109/+247
| |\ \ | | |/ | |/| | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| | * ARM: tegra: colibri_t20: fix nand pinmuxMarcel Ziswiler2015-03-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Pingroup ATC seems to come out of reset with config set to NAND, so we need to explicitly configure some other function to this group in order to avoid clashing settings. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BITLucas Stach2015-03-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: update colibri_t20 configurationMarcel Ziswiler2015-03-30-4/+27
| | | | | | | | | | | | | | | | | | | | | Bring the Colibri T20 configuration in-line with Apalis/Colibri T30. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: fix colibri_t20 asix resetMarcel Ziswiler2015-03-30-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Fix ASIX USB to Ethernet chip reset. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-08-27 18:41:51 +0000