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* 86xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+2
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* 85xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+9
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-63/+102
| | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: remove unused config definitionDave Liu2008-10-24-18/+0
| | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+16
| | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
| | | | | | | Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix strmhz(): avoid printing negative fractionsWolfgang Denk2008-10-22-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig functionRichard Retanubun2008-10-21-5/+0
| | | | | | | | This is done to allow other 83XX based platforms which also have UPM (e.g. 8360) to configure and use their UPM in u-boot. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-4/+4
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov2008-10-21-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+47
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+125
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add TSECs' HRCWH masks for MPC837x processorsAnton Vorontsov2008-10-21-0/+2
| | | | | | | We'll use these masks to parse TSEC modes out of HRCWH. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: serdes: add forgotten shifts for rfcksAnton Vorontsov2008-10-21-6/+6
| | | | | | | | | | The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix serdes setup for the MPC8378E boardsAnton Vorontsov2008-10-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-26/+38
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* FDT: don't use private kernel header filesWolfgang Denk2008-10-21-14/+25
| | | | | | | | | | | | | | On some systems (for example Fedora Core 4) U-Boot builds with the following wanrings only: ... In file included from /home/wd/git/u-boot/include/libfdt_env.h:33, from fdt.c:51: /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead! This patch fixes this problem. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-330/+1368
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| * ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setupStefan Roese2008-10-21-0/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+59
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+547
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Update configs for Netstal boardsNiklaus Giger2008-10-21-275/+292
| | | | | | | | | | | | | | | | | | | | I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-19/+384
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-21-54307/+58233
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| * | ppc4xx: PPC44x MQ initializationStefan Roese2008-10-17-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | TQM8260: environment in flash instead EEPROM, baudrate 115kWolfgang Denk2008-10-21-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | 85xx: Fix compile warning in mpc8536ds.cKumar Gala2008-10-21-1/+0
| | | | | | | | | | | | | | | | | | | | | mpc8536ds.c: In function 'is_sata_supported': mpc8536ds.c:615: warning: unused variable 'devdisr' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-98/+98
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-83/+112
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | strmhz(): Round numbers when printing clock frequenciesWolfgang Denk2008-10-21-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Round clock frequencies for printing. Many boards printed off clock frequencies like 399 MHz instead of the exact 400 MHz because numberes were not rounded. This is fixed now. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFGTimur Tabi2008-10-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. The changelog for that commit is also wrong, as it says "bit 28" when it should be "bit 24". Signed-off-by: Timur Tabi <timur@freescale.com>
* | | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-55608/+61684
|\ \ \ | | |/ | |/| | | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * | Merge 'next' branchWolfgang Denk2008-10-18-54298/+58094
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | mgcoge: add redundant environment sectorHeiko Schocher2008-10-18-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * | mgsuvd: update size of environmentHeiko Schocher2008-10-18-3/+1
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * | Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+45
| | | | | | | | | | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | * | Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * | Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * | Add cpu/8xxx to TAGS_SUBDIRSEd Swarthout2008-10-18-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * | fsl_law clear enable before changing.Ed Swarthout2008-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * | mpc8572 additional end-point modeEd Swarthout2008-10-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * | 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * | pixis do not print long help if not configuredEd Swarthout2008-10-18-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * | Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | Add DDR options setting on MPC8641HPCN boardHaiying Wang2008-10-18-36/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * | Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-29/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * | Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
| | | | | | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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