| Commit message (Collapse) | Author | Age | Lines |
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1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
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The i.MX6QP has a PRG module, need to enable its clock for using
IPU.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 089f399ea07db79d6bca8fdc08b442b59eb55feb)
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Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 96e13b57ead3ed00c3a32c5373c7a2a876947f99)
Conflicts:
arch/arm/cpu/armv7/mx6/hab.c
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Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference.
At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35)
Conflicts:
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h
include/configs/mx6_common.h
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Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit aa8a38edb67d4d1375d10bee9bf46557369fb5c4)
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Add new cpu type for i.MX6DQP and providing a dynamical
detecting function.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ccf3b130d71cf3dd9a97d3bb424931bf6bd7e8c0)
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Enable 1.8V on PHY control, so that Gigabit PHY operation
can be functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit a17f1300a1b6d3b46a090baa84ba2fef104a1af6)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We should use CONFIG_FSL_QSPI, but not CONFIG_QSPI
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Need to check value of spi_setup_slave and spi_setup_slave_fdt.
If their return value 'bus' is NULL, there is no need to pass it
to following spi_flash_probe_tail.
If 'bus' is null, the original function flow is as following:
spi_flash_probe
|->spi_setup_slave
|->spi_probe_bus_tail
|->spi_flash_probe_slave
|->spi_free_slave
Alougth check the pointer in spi_free_slave is ok, checking the return value
of spi_setup_slave and spi_setup_slave_fdt is better.
Before this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
SF: Failed to set up slave
data abort
pc : [<fff66dcc>] lr : [<fff7628c>]
reloc pc : [<87814dcc>] lr : [<8782428c>]
sp : fdf4fcf0 ip : e630396c fp : fe0d0888
r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00
r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c
r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
"
After this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
Failed to initialize SPI flash at 0:2
"
No data abort using this patch.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Upgrade to upstream way, using power_init_board.
Add pfuze300 support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add CONFIG_CMD_FASTBOOT
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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If in mmc_send_op_cond, OCR_BUSY is set in CMD1's response, then
state is transfered to Ready state, and there is no need to send
CMD1 again. Otherwise following CMD1 will recieve no response, or
timeour error from driver such as fsl_esdhc.c.
If not into Ready state in previous CMD1, then continue CMD1 command.
In mmc_complete_op_cond, we use the value mmc->op_cond_response
from mmc_send_op_cond, since there should be no CMD1 command between
mmc_send_op_cond and mmc_complete_op_cond
Before fixing this, uboot log shows:
"
CMD_SEND:0
ARG 0x00000000
MMC_RSP_NONE
CMD_SEND:8
ARG 0x000001AA
MMC_RSP_R1,5,6,7 0x18EC1504
CMD_SEND:55
ARG 0x00000000
MMC_RSP_R1,5,6,7 0x18EC1504
CMD_SEND:0
ARG 0x00000000
MMC_RSP_NONE
CMD_SEND:1
ARG 0x00000000
MMC_RSP_R3,4 0x00FF8080
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0xC0FF8080 --> Already OCR_BUSY set
CMD_SEND:1
ARG 0x40300000
MMC_RSP_R3,4 0x0096850A --> Failed CMD1
MMC init failed
"
Using this patch, this issue is fixed, emmc can be detected correctly.
This issue exists on mx7dsabresd and mx7d_12x12_lpddr3_arm2 board.
Upstream Patchwork:
https://patchwork.ozlabs.org/patch/451775/
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit ca4113da25b42bce44a2e7998966a47352f11613)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Change QSPI FLASH vendor config from to MACRONIX, otherwise the flash
device can't be recognized.
Also change default sf probe parameter to 0:0 which means bus 0, cs 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f250cf69571851eb092252275418daf8de11a68e)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update board codes to support GPMI NAND flash. Since the GPMI NAND needs
board rework, it is disabled at default. Two ways to enable GPMI NAND:
1. Define CONFIG_SYS_BOOT_NAND for NAND boot case
2. Modify the line 306 in mx7dsabresd.h from QSPI to NAND.
#define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */
to
#define CONFIG_SYS_USE_NAND /* Enable the NAND flash at default */
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5db03facf3add6a95728bc97ac2300003a103932)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 42f42939bbd8161ce283a6af326d0f313cc4c36c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 9c50677dac30085742ef216b9f2e19308e123d2b)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update APBH-DMA driver and head files with definitions for CONFIG_MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 07299056426f1f25aab51ab5531c4846d4c7560f)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable android fastboot, recovery, booti features for mx7d sabresd
board by using new build target: mx7devkandroid_config
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit bfc2b467ddac9c6eccb3f39aad3663a959546b64)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
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When booting in eMMC fast boot, the uboot v2013.04 always hangs.
The root cause is that MMC host does not exit from boot mode after
bootrom loading image. So the first command 'CMD0' sent
in uboot will pull down the CMD line to low and cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Signed-off-by: Ye Li <b37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 2ead2f9501c6d2571e0f5365bd808ed7c73257ef)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
drivers/mmc/fsl_esdhc.c
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Update driver codes and registers define for MX7. Implement udc callback
function in MX7 arch.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e55c4f7bf5a66b34c2d01c42bac667cb3789b0c1)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add udc and fastboot support
We did not use the upstream way.
Currently use CI_UDC and USB_GAGDET of upstream can make fastboot work,
but lack of flash operation, so we still use our way.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add missed included header file crm_regs.h
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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LCD_MONOCHROME is removed in commit f4469f50b0367820121ef2d313517d422ed70e1d.
Add related code back to support epdc.
In this patch, also include crm_regs.h in mx6slevk.c to make epdc code
be compiled ok.
COLOR_MASK is also added from commit a7de2953f51e70754190d3516167d58d27d17219
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add thermal driver for mx7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Change macro name to make driver support more platforms.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This patch is from commit c83c6cc7dedf9759bf193044ff5c3572d5f6afd2
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add CONFIG_SYS_MALLOC_F and CONFIG_SYS_MALLOC_F_LEN to support
correctly detect temperature sensor.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Modify Makefile to support MX7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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EPDC board contain a elan touch screen, this screen is a i2c
slave. If this EPDC board connect to i.MX6SL-EVK board, after
uboot boot up, if we do i2c operation, like i2c probe, then
the i2c bus block. This is due to the elan touch screen i2c slave.
This device needs to do some initialization opearation before its
i2c operation, otherwise this i2c device pull down the i2c clk line,
and make the i2c bus hang. This means elan needs a special flow on
i2c before its address is acked, otherwise the i2c bus will be hang.
This patch is a workaround, it add a void function which is defined
as a weak symbol in i2c driver, and it is called before every i2c
operation. In mx6slevk, this function was overwrite to execute elan
initialization. So that, for mx6slevk board, it will initialize
elan before every i2c operation, but for other boards, it just work
as before.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
(cherry picked from commit 4c587b29c423ce61b2471ed20f31ff533d9d8a39)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
board/freescale/mx6slevk/mx6slevk.c
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* Update DCD table for lpddr3 @400Mhz
* Boot kernel linux and run memtester for memory stress
memtester 1G 100000
Signedoff-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
(cherry picked from commit 7cbab5830d486733a691be104cbc2be494b00776)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable SNVS clock in clock_init function as default enabled clock.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df1e45b3098f737d68517c51032472d12fd87666)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add i.MX7D SABRESD board BSP codes, with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabresd_config
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 3bf52a153e2964d4fdc17f0e8cb816686cbb6c2b)
Conflicts:
boards.cfg
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The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which
does not have power and DDR reset. So the peripherals and DDR may meet problem.
When using the internal WDOG reset on i.MX7D ARM2 boards,
we meets two DDR issues:
1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode
does not become to normal.
2. On 19x19 ARM2, the reset always brings system to USB download because the
DDR3 turns to unstable.
On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives
a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and
enable WDOG_B signal output in WDOG WCR register.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes, configuration head file and build target for
19x19 DDR3L ARM2 board with basic functions:
ENET2, I2C, SD/eMMC/MMC, USB, QSPI, ECSPI, pfuze3000 PMIC.
Build target: mx7d_19x19_ddr3_arm2_config
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 58fd869e3097b7461fbfae3d94e3ebbd30ae2474)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
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Implement the auxiliary core booting for Cortex M4 on i.MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit c1c8ba37d87493c16ec1a12bc36d47f909e0e733)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Fix the warning below by adding function declare:
drivers/video/mxsfb.c: In function 'mxs_lcd_init':
drivers/video/mxsfb.c:92:2: warning: implicit declaration of
function 'mxs_set_lcdclk' [-Wimplicit-function-declaration]
mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock));
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 615af07d960d9ec17708fb1712b2362dbaeab121)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes, configuration head file and build target for
12x12 LPDDR3 ARM2 board with basic functions:
ENET, I2C, SD/eMMC/MMC, USB, LCD Splash screen, QSPI, ECSPI,
pfuze3000 PMIC.
Note: pmic and video is still not upstream way
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ac0d51ef07fdec880e6da318c08d521506640efa)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
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Add mx7d_arm2.h for common part of all i.MX7D arm2 boards
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 6cc15cf8c4e1f9a08130c5e232f23af75407fa50)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add common head file mx7_common.h for all i.MX7 platform
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e38c9a7a543890e0879f89627a3f404d8068d602)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since rom code supports clear bit and check data command, and new ddrc
needs such commands, add clear bit and check data command in imximage.c.
CHECK_DATA 4 xxxx bit
This command is dead loop until bit set at address xxxx.
CLR_BIT 4 xxxx bit
This command is to clear bit at address xxxx.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 257600d197bf9a58a2b8d08419296aaf901d850d)
Conflicts:
tools/imximage.c
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Since from mx7, we use fixed IVT offset for all boot devices.
Introduce a new configuration CONFIG_IMX_FIXED_IVT_OFFSET for this.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 88e0a3552b08627b18d98380a32dbafacb18854b)
Conflicts:
tools/imximage.h
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DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit dddb52ebdc6c4919da0103a364563dbe2c100874)
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DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 13cdb96bc52b3079ba91a08c1704307e5598ee59)
Conflicts:
drivers/mmc/fsl_esdhc.c
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Add mx7 in driver/watchdog/Makefile to support watchdog driver for imx7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 19d698109fd136586b292430989e0f6edb723db6)
Conflicts:
drivers/watchdog/Makefile
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There are two FEC controller on MX7, and each MDIO bus can be shared
with other. So add a configuration for this case.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit d31b4fcc6175b1bc9a2cf672678da212b133af17)
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Ocotp of i.MX7D has different operation rule.
This patch is to add support for i.MX7D ocotp.
Note:
DIV_ROUND is changed to DIV_ROUND_CLOSEST
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit d0c3564b6a0f430254edcd8db1f33588bbeccb08)
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Add i2c support for i.MX7D.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b52cb9d40e71305b7a11b0bbc68fddd8e84e3b17)
Conflicts:
drivers/i2c/mxc_i2c.c
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Add usb driver for i.MX7D.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit c78f52798d6b7dda775d272c3ccb9899e548d3d6)
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Add CONFIG_MX7 for mxc gpio driver
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 6e3f8dc68f1606cbbcdb4997fc0bdf1ac8a3f3b6)
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Add mx7_plugin.S to support building plugin boot image.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 8d15f44ca0c2d694b87eb6ab6db5f27496924b4a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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