| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
|
|
| |
The purpose of this build target is to do SPL over USB RNDIS. We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets. This brings us well under size limit again.
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|\
| |
| |
| |
| |
| |
| | |
Conflicts:
README
Signed-off-by: Tom Rini <trini@konsulko.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
In order to work with our downstream U-Boot environment and update
scripts add support for the following miscellaneous commands:
CONFIG_CMD_SETEXPR
CONFIG_FAT_WRITE
Increase the console I/O and print as well as argument buffer sizes:
CONFIG_SYS_CBSIZE
CONFIG_SYS_PBSIZE
CONFIG_SYS_BARGSIZE
Increase the maximum number of arguments allowed:
CONFIG_SYS_MAXARGS
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Now with all the Tegra PCIe and Intel E1000 gigabit Ethernet driver
updates being merged actually make use of it.
While at it get rid of the USB networking support which now does not
make much sense any longer.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This fixes the MMC/SD card detect GPIOs for Apalis T30 which got broken
by the following commit:
2b2b50bc8748 "dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs"
While at it also re-add the comments describing which particular
Apalis/Colibri pins those GPIOs are on.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All boards with a SPI interface have a suitable spi alias except Apalis
T30. Add these missing aliases just as the following commit did for the
others:
d2f60f93325a "dm: tegra: dts: Add aliases for spi on tegra30 boards"
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| | |
This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Tegra210 has a per-pin option named e_io_hv, which indicates that the
pin's input path should be configured to be 3.3v-tolerant. Add support
for this.
Note that this is very similar to previous chip's rcv_sel option.
However, since the Tegra TRM names this option differently for the
different chips, we support the new name so that the code exactly matches
the naming in the TRM, to avoid confusion.
This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
T210 support HSM and Schmitt options in the pinmux register (previous
chips placed these options in the drive group register). Update the
code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Tegra210 moves some bits around in the pinmux registers. Update the code
to handle this.
This doesn't attempt to address the issues with the group-to-group varying
drive group register layout mentioned earlier. This patch handles the
SoC-to-SoC differences in the mux register layout.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
On some future SoCs, some per-drive-group features became per-pin
features. Move all type definitions early in the header so they can
be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
On some future SoCs, some of the per-drive-group features no longer
exist. Add some ifdefs to support this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Tegra's drive group registers have a remarkably inconsistent layout. The
current U-Boot driver doesn't take this into account at all. Add a
comment to describe the issue, so at least anyone debugging the driver
will be aware of this. To solve this, we'd need to add a per-drive-group
data structure describing the layout for the individual register. Since
we don't set up too many drive groups in U-Boot at present, this
hopefully isn't causing too much practical issue. Still, we probably need
to fix this sometime.
Wth Tegra210, the register layout becomes almost entirely consistent, so
this problem partially solves itself over time.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
The new spreadsheet sets TRISTATE for any input-only pins. This only works
correctly if the global CLAMP bit is not set, so the Jetson TK1 board code
has been adjusted accordingly. Apparently syseng have changed their mind
since the previous advice that this needed to be set:-/
This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded
from https://developer.nvidia.com/hardware-design-and-development.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
When the CPU is in non-secure (NS) mode (when running U-Boot under a
secure monitor), certain actions cannot be taken, since they would need
to write to secure-only registers. One example is configuring the ARM
architectural timer's CNTFRQ register.
We could support this in one of two ways:
1) Compile twice, once for secure mode (in which case anything goes) and
once for non-secure mode (in which case certain actions are disabled).
This complicates things, since everyone needs to keep track of
different U-Boot binaries for different situations.
2) Detect NS mode at run-time, and optionally skip any impossible actions.
This has the advantage of a single U-Boot binary working in all cases.
(2) is not possible on ARM in general, since there's no architectural way
to detect secure-vs-non-secure. However, there is a Tegra-specific way to
detect this.
This patches uses that feature to detect secure vs. NS mode on Tegra, and
uses that to:
* Skip the ARM arch timer initialization.
* Set/clear an environment variable so that boot scripts can take
different action depending on which mode the CPU is in. This might be
something like:
if CPU is secure:
load secure monitor code into RAM.
boot secure monitor.
secure monitor will restart (a new copy of) U-Boot in NS mode.
else:
execute normal boot process
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All boards need CONFIG_BOARD_EARLY_INIT_F, and many actively need
CONFIG_BOARD_LATE_INIT. Move both of these into tegra-common.h so that
board config headers don't need to repeatedly define them.
Later commits will add new code in board_late_init() which applies to
all boards, so CONFIG_BOARD_LATE_INIT should be enabled for all Tegra
boards.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Some systems have so much RAM that the end of RAM is beyond 4GB. An
example would be a Tegra124 system (where RAM starts at 2GB physical)
that has more than 2GB of RAM.
In this case, we want gd->ram_size to represent the actual RAM size, so
that the actual RAM size is passed to the OS. This is useful if the OS
implements LPAE, and can actually use the "extra" RAM.
However, we can't use get_ram_size() to verify the actual amount of RAM
present on such systems, since some of the RAM can't be accesses, which
confuses that function. Avoid calling get_ram_size() when the RAM size
is too large for it to work correctly. It's never actually needed anyway,
since there's no reason for the BCT to report the wrong RAM size.
In systems with >=4GB RAM, we still need to clip the reported RAM size
since U-Boot uses a 32-bit variable to represent the RAM size in bytes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
size_mb is used to hold a value that's sometimes KB, sometimes MB,
and sometimes bytes. Use separate correctly named variables to avoid
confusion here. Also fix indentation of a conditional statement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Some systems have so much RAM that the end of RAM is beyond 4GB. An
example would be a Tegra124 system (where RAM starts at 2GB physical)
that has more than 2GB of RAM.
In this case, we can gd->ram_size to represent the actual RAM size, so
that the actual RAM size is passed to the OS. This is useful if the OS
implements LPAE, and can actually use the "extra" RAM.
However, U-Boot does not implement LPAE and so must deal with 32-bit
physical addresses. To this end, we enhance board_get_usable_ram_top() to
detect the "over-sized" case, and limit the relocation addres so that it
fits into 32-bits of physical address space.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Nowadays generic CFI code properly detects the ED Mini V2's
Macronix MC29LV400CB flash chip, therefore we can drop the
CONFIG_FLASH_CFI_LEGACY option and associated settings and code.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.
Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
| |
| |
| |
| | |
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
| |
| |
| |
| | |
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
| |\ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch adds support for handling 828024 and 826974 erratas
for Cortex-A57 cores present on LS2085A SoC.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.
As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.
Later on this framework can be extended to include other
erratas.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Fix a typo in board/sunxi/Kconfig which caused VIDEO_LCD_PANEL_I2C to be
enabled on all sunxi boards. Also fix a compile error which shows up once
VIDEO_LCD_PANEL_I2C is actually disabled on most boards as it should be.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch add support for Wexler TAB7200 tablet.
The Wexler TAB7200 is a A20 based tablet with 7 inch display(800x480),
capacitive touchscreen(5 fingers), 1G RAM, 4G NAND, micro SD card slot,
mini HDMI port, 3.5mm audio plug, 1 USB OTG port and 1 USB 2.0 port.
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Use the AXP223 PMIC to detect VBUS for musb otg support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This enables the musb glue layer to use the AXP221's VBUS detection
function to check for VBUS. This fixes otg support on the A23 q8h
tablets.
Note that u-boot never calls musb_shutdown(), so once VBUS is enabled,
it is never disabled until the system is powered off, or the OS does
so. This can be used to our advantage to keep VBUS powered into the
OS, where support for AXP221 is not available yet.
Fixes: 52defe8f6570 ("sunxi: musb: Check Vbus-det before enabling otg port power")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Some of the AXP PMICs support VBUS detection, i.e. checking whether
VBUS power input is available and usable (supplied by an external
source). A few boards use this instead of a separate GPIO to detect
VBUS on USB OTG.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Orange Pi Mini is an A20 based development board featuring 1G RAM, HDMI,
1Gbit ethernet, USB wifi, SATA, 2 sdcard slots (use the top one for booting),
2 USB 2.0 A receptacles, a micro USB B receptacle (otg) and a 3 ring 3.5 mm
jack connector for A/V.
Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Orange Pi is an A20 based development board featuring 1G RAM, HDMI & VGA,
1Gbit ethernet, USB wifi, SATA, 4 USB 2.0 A receptacles, a micro USB B
receptacle (otg) and a 3 ring 3.5 mm jack connector for A/V.
Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Wits Pro A20 DKT is an A20 Development KiT with 1G RAM, 4G NAND, sdio wifi,
1Gbit ethernet, 1024x768 lcd screen with ft5x_ts touchscreen and a ton of
IO connectors.
Note there seem to be multiple sdcard slots on the board (4 in total), but
other then mmc0 none of these are hooked up by default, there is a ton of
dip-switches which likely allow hooking some of these up, but the documentation
of the board only describes the use of a fraction of them, so for now we
only support mmc0.
Also see: http://www.merrii.com/en/pla_d.asp?id=163
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Forfun Q88DB is an A13 tablet in the common Q8 format.
Features are 512MB RAM, 4GB NAND, 7" Display, RTL8188 Wifi, 2 cameras.
For more details see: http://linux-sunxi.org/Forfun_Q88DB
Signed-off-by: Jens Lucius <info@jenslucius.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Mele I7 is a Allwinner based Android TV box.
It features a A31 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
SPDIF, IrDA, 3 USB A, 1 USB micro OTG and Wireless LAN.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The MK808C is a Allwinner based Android TV dongle.
It features a A20 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
1 USB A, 1 USB mini OTG, Bluetooth and Wireless LAN.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity can
be extended up to 32GB with a MicroSD card. The external connectors are: 2x
USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female,
SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired to
power) and an programmable green led. On the board there is also an unpopulated
IR receiver and the UART. The devices is equipped with an AXP209 PMU.
For more details see: http://linux-sunxi.org/Jesurun_Q5
Signed-off-by: Gábor Nyers <gnyers@opensuse.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The tpr3 (timing skew) parameter is used in all supported versions of
the sunxi DRAM controller, but it was only enabled for sun4i in
47e3501a76894f4ba08bc61f33774bd5d39ff464.
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Added support to disable the start of application by using
a environment variable autostart
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|