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* Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-40/+1088
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| * sandbox: spi: Enable new spi/sf layersMike Frysinger2013-12-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | We want to test SPI flash code in the sandbox, so enable the new drivers and the 'sf test' command. This command is used to validate the sandbox SPI / SPI flash implementation, so enable it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: spi: Add new SPI flash driverMike Frysinger2013-12-09-1/+605
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a SPI flash driver which simulates SPI flash clients. Currently supports the bare min that U-Boot requires: you can probe, read, erase, and write. Should be easy to extend to make it behave more exactly like a real SPI flash, but this is good enough to merge now. sjg@chromium.org added a README and tidied up code a little. Added a required map_sysmem() for sandbox. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: spi: Add SPI emulation busMike Frysinger2013-12-09-0/+280
| | | | | | | | | | | | | | This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi: Add device tree binding for SPI busSimon Glass2013-12-09-0/+92
| | | | | | | | | | | | This was obtained from Linux 3.12 commit 5e01dc7b26. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-17/+77
| | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Rename sb_cmdline_option to sandbox_cmdline_optionSimon Glass2013-12-09-22/+24
| | | | | | | | | | | | | | | | | | | | The new name is longer but more clearly related to sandbox. This is in a separate patch within the same series since some comments on the SPI series rely on it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2013-12-10-18/+72
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| * | mmc: add Faraday FTSDC021 SDHCI controller supportKuo-Jung Su2013-12-08-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTSDC021 is a controller which is compliant with SDHCI v3.0, SDIO v2.0 and MMC v4.3. However this driver is only verified with SD memory cards. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> CC: Andy Fleming <afleming@gmail.com>
| * | powerpc: mmc: Add corenet devices support in esdhc splPriyanka Jain2013-12-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing eSDHC SPL framework assumes booting from sd-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mmc/dwmmc: modify FIFO threshold only if value explicitly setAlexey Brodkin2013-12-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If platform provides "host->fifoth_val" it will be used for initialization of DWMCI_FIFOTH register. Otherwise default value will be used. This implementation allows: * escape unclear and recursive calculations that are currently in use * use whatever custom value for DWMCI_FIFOTH initialization if any particular SoC requires it Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mmc: dw_mmc: remove the exynos specific code in dw-mmc.cJaehoon Chung2013-12-08-10/+17
| |/ | | | | | | | | | | | | | | | | | | | | dw-mmc.c is the general driver file. So, remove the exynos specific code at dw-mmc.c. Instead, exynos specific cod can be move into exynos-dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-12-10-317/+474
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| * | i2c: samsung: register i2c busses for Exynso5420 and Exynos5250Naveen Krishna Ch2013-12-06-48/+182
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels on Exynos5420 and Exynos5250 and also adds support for init function for hsi2c channels Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | arm: omap: i2c: don't zero cnt in i2c_writeNikita Kiryanov2013-12-05-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3 based devices. This seems to be related to the following advisory which apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as OMAP4430 TRM: Advisory: I2C Module Does Not Allow 0-Byte Data Requests Details: When configured as the master, the I2C module does not allow 0-byte data transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause undefined behavior. Workaround(s): No workaround. Do not use 0-byte data requests. The writes in question are unnecessary from a functional point of view. Most of them are done after I/O has finished, and the only one that preceds I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before actual data transmission takes place. Therefore, remove all writes that zero the cnt register. Cc: Heiko Schocher <hs@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Tom Rini <trini@ti.com> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Enric Balletbo Serra <eballetbo@gmail.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com>
| * | cmd_eeprom: bug fix for i2c read/writeKuo-Jung Su2013-12-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The local pointer of address (i.e., addr) only gets referenced under SPI mode, and it won't be appropriate to pass only 1-byte addr[1] to i2c_read/i2c_write while CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1. 1. In U-boot's I2C model, the address would be re-assembled to a byte string in MSB order inside I2C controller drivers. 2. The 'CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW' option which could be found at soft_i2c.c is always turned on in cmd_eeprom.c, the addr[0] always contains the device address with overflowed MSB address bits. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com>
| * | i2c: fti2c010: serial out r/w address in MSB orderKuo-Jung Su2013-12-05-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B), the r/w address should be serial out in MSB order. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | i2c: fti2c010: migrate to new i2c modelKuo-Jung Su2013-12-05-166/+133
| | | | | | | | | | | | | | | | | | | | | Replace the legacy i2c model with the new one. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | i2c: fti2c010: cosmetic: coding style cleanupKuo-Jung Su2013-12-05-15/+16
| | | | | | | | | | | | | | | | | | | | | Coding style cleanup Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | driver:i2c:s3c24x0: fix clock init for hsi2cPiotr Wilczek2013-12-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix clock value initialisation for Exynos other than Exynos5 for hsi2c. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Heiko Schocher <hs@denx.de>
| * | driver:i2c:s3c24x0: adapt driver to new i2cPiotr Wilczek2013-12-05-121/+170
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-06-107/+22
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| * | blackfin: Do not generate unused header bootrom-asm-offsets.hMasahiro Yamada2013-12-06-66/+0
| | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | spi: bfin_spi: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: soft-i2c: No need to define blackfin specific soft i2c operationsSonic Zhang2013-12-06-27/+2
| | | | | | | | | | | | | | | | | | | | | Use default GPIO operations. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | blackfin: Add missing macro CONFIG_BFIN_SERIALSonic Zhang2013-12-06-0/+6
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: If none ADI_GPIOX macro is defined, use ADI_GPIO1 as defaultSonic Zhang2013-12-06-2/+2
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: Use ADI_GPIO2 driver other than the default ADI_GPIO1Sonic Zhang2013-12-06-0/+2
| |/ | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | powerpc/mpc8349: Use generic mpc85xx DDR driverYork Sun2013-12-04-3/+2
| | | | | | | | | | | | | | | | | | | | MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/t2080qds: undef CONFIG_FSL_DDR_INTERACTIVEShengzhou Liu2013-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Usually CONFIG_FSL_DDR_INTERACTIVE feature is used for debug. we would not enable this by default to save the limited space of u-boot. This avoid following compiling error: section .bootpg loaded at [00000000effff000,00000000effff577] overlap ssection .data loaded at [00000000efff31b8,00000000f00010c7] u-boot: section .bootpg lma 0xeffff000 adjusted to 0xf00010c8 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | T4240: Address T4240/T4160 Rev2.0 DDR clock changeZang Roy-R619112013-12-04-0/+8
| | | | | | | | | | | | | | | | | | MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc: spiflash:Add corenet devices support in eSPI SPLPriyanka Jain2013-12-04-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROMPo Liu2013-12-04-0/+13
| | | | | | | | | | | | | | | | | | | | Currently, there is only one EEPROM on c29xpcie board which is AT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc/p1010rdb:modify the mtest start_addressZhao Qiang2013-12-04-1/+1
| | | | | | | | | | | | | | | | | | In new board P1010RDB-PB, the interrupt vector table is at the start of memory. So if the start_address needs to be set a proper value. Signed-off-by: Zhao Qiang <B45475@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc/corenet: CPC1 speculation disableDave Liu2013-12-04-0/+4
|/ | | | | | | | | | In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'serial' of git://git.denx.de/u-boot-microblazeTom Rini2013-12-02-4/+0
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| * serial: zynq: Remove unused #definesSoren Brinkmann2013-12-02-4/+0
| | | | | | | | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: trini, uboot
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-12-02-3/+25
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| * | malta: set CONFIG_SYS_BOOTM_LEN to 64MBPaul Burton2013-11-26-0/+1
| | | | | | | | | | | | | | | | | | | | | Allow a larger kernel binary to be decompressed - the default 8MB can become limiting on a Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | malta: enable PIIX4 SERIRQPaul Burton2013-11-26-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | malta: correct UART baudratePaul Burton2013-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in a UART at 115200 baud, thus the x16 clock rate is 115200 * 16. Previously the divider was left at 0 which led to a rate of 38400 baud regardless of CONFIG_BAUDRATE or the baudrate environment variable. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | mips: don't hardcode Malta env baudratePaul Burton2013-11-26-2/+4
| |/ | | | | | | | | | | | | | | | | The baudrate passed to Linux in the environment was hardcoded at 38400. Instead pass the correct baudrate from global data, allowing Linux to correctly inherit the baudrate used by U-boot when console setup is not explicitly specified. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Blackfin: remove executable permission of AWK scriptMasahiro Yamada2013-12-02-0/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-735/+3595
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| * t2080qds/ramboot: enable PBL tool for t2080qdsShengzhou Liu2013-11-25-0/+55
| | | | | | | | | | | | | | | | Add the default RCW(SerDes 0x66_0x16) and PBI configure file for T2080QDS board, so we can use PBL tool to generate the ramboot image to support boot from NAND/SPI/SD. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/t2080qds: add support for t2080qds boardShengzhou Liu2013-11-25-0/+2126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-1/+512
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-6/+48
| | | | | | | | | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-13/+13
| | | | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-10-12 11:07:59 +0000