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* MX28: Fix up the MMC driver DMA modeMarek Vasut2012-09-01-2/+8
| | | | | | | | | | | The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1. Also, it was using SSP0 DMA channel for all SSP devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCsOtavio Salvador2012-09-01-1/+1
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Clarify why we poweroff in case of brownout in 5v conflictOtavio Salvador2012-09-01-0/+4
| | | | | | | | If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable but this wasn't clear on code so a comment has been added to clarify it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador2012-09-01-116/+116
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-189/+188
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register acessor macros with 'mxs' prefixOtavio Salvador2012-09-01-529/+529
| | | | | | | As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: reorganize source directory for easy sharing of code in i.MXS SoCsOtavio Salvador2012-09-01-14/+14
| | | | | | | | | Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* mx28evk: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX28: use a clear name for DDR2 initializationOtavio Salvador2012-09-01-6/+6
| | | | | | | | | The mx28 prefix has been added to the initialization data and function so it is clear by which SoC it is used as i.MX233 will have a specific one. While on that, we also change it to static. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* Add support for Bluegiga APX4 Development KitVeli-Pekka Peltola2012-09-01-0/+618
| | | | | | | | | | This adds support for Bluegiga APX4 Development Kit. It is built around Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC, RTC and USB. APX4 has only one ethernet port. Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Cc: Stefano Babic <sbabic@denx.de>
* MX28: extend print_cpuinfo() to use chip informationOtavio Salvador2012-09-01-2/+40
| | | | | | | The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* MX28: SPI: Add DMA transfer supportMarek Vasut2012-09-01-1/+116
| | | | | | | | | | | | | | | | | The DMA transfers happen only if the transfered data are larger than 512 bytes. Otherwise PIO is used. This is a small speed optimization. The DMA transfer doesn't work if unaligned transfer is requested due to the limitation of the DMA controller. This has to be fixed by introducing generic bounce buffer. Therefore the DMA feature is now disabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Pull out the PIO transfer functionMarek Vasut2012-09-01-33/+41
| | | | | | | | | | | Pull out all the PIO transfer logic into separate function, so DMA can be added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Refactor spi_xfer a bitMarek Vasut2012-09-01-10/+22
| | | | | | | | | | This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* imx: Use a clear identification of an unidentified CPU typeOtavio Salvador2012-09-01-2/+2
| | | | | | | | | | In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* at91: Add support for taskit AT91SAM9G20 boards.Markus Hubig2012-09-01-0/+654
| | | | | | | | | | This adds support for the AT91SAM9G20 boards by taskit GmbH. Both boards, Stamp9G20 and PortuxG20, are integrated in one file. PortuxG20 is basically a SBC built around the Stamp9G20. Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
* Enable the EMAC clock in at91_macb_hw_init().Markus Hubig2012-09-01-0/+4
| | | | | | Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* MAINTAINERS: fix Andreas Bießmann AVR32 entryAndreas Bießmann2012-09-01-1/+3
| | | | | | | The grasshopper board is a avr32 based device and belongs therefore to the avr32 section. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* MAINTAINERS: fix entry of Ilko IlievAndreas Bießmann2012-09-01-6/+6
| | | | | | These boards have ARM cores, move to the ARM section. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm : Atmel : add at91sam9x5ek board supportBo Shen2012-09-01-4/+1043
| | | | | | | | | | | | Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: Bo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* doc/git-mailrc: update at91 and avr32Andreas Bießmann2012-09-01-2/+3
| | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* am335x_evm: enable SMSC PHY driverIlya Yanok2012-09-01-0/+1
| | | | | | | | Beaglebone uses SMSC PHY which works incorrectly with generic PHY driver so enable SMSC PHY driver to fix networking problems on Beaglebone. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* OMAP3: fix DRAM size for IGEP-based boards.Enric Balletbò i Serra2012-09-01-6/+6
| | | | | | | | The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the LPDDR memory consist on two dies of 256MiB. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
* DaVinci DA8xx: fix set_cpu_clk_info()Laurence Withers2012-09-01-9/+14
| | | | | | | | | | | | | | | | | | | | | | For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as: [...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Hadli, Manjunath <manjunath.hadli@ti.com> Cc: Heiko Schocher <hs@denx.de>
* DaVinci DA8xx: replace magic number for DDR speedLaurence Withers2012-09-01-1/+4
| | | | | | | | | | Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* DaVinci DA850: UART2 clock ID comes from ASYNC3Laurence Withers2012-09-01-1/+3
| | | | | | | | | | On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* DaVinci DA8xx: tidy up clock ID definitionLaurence Withers2012-09-01-16/+40
| | | | | | | | | | | Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
* doc/git-mailrc: Update 'ti' aliasTom Rini2012-09-01-1/+1
| | | | | | Remove Sandeep, thanks for all the hard work! Signed-off-by: Tom Rini <trini@ti.com>
* dm: Move OMAP GPIO driver to drivers/gpio/Marek Vasut2012-09-01-3/+19
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* dm: Select CONFIG_SPL_GPIO_SUPPORT on OMAPMarek Vasut2012-09-01-0/+6
| | | | | | | | | | | | | This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework pinmux functionsTom Rini2012-09-01-78/+68
| | | | | | | | | | - Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx evm: Add CONFIG_CMD_EEPROM and relatedTom Rini2012-09-01-9/+8
| | | | | | | am33xx boards have at least one eeprom and in the case of beaglebones with capes, more. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support for TI AM335x StarterKit EVMTom Rini2012-09-01-2/+50
| | | | | | | | | | - Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove board/ti/am335x/evm.cTom Rini2012-09-01-200/+174
| | | | | | | | | The intention has always been (and boards are to support) an i2c EEPROM that will identify what hardware they are, allowing a single binary to support multiple boards. As such, remove the 'evm.c' file as there is nothing EVM centric in it currently, only SoC peripheral configuration. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-01-0/+60
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_ddr to make DDR3 support easier.Tom Rini2012-09-01-14/+23
| | | | | | | | In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move some variables in emif4.c, mark them static.Tom Rini2012-09-01-4/+3
| | | | | | We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct and clean up ddr_regs structTom Rini2012-09-01-34/+20
| | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-01-35/+7
| | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-01-27/+8
| | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-01-78/+31
| | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-01-42/+15
| | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini2012-09-01-4/+3
| | | | | | | | | - Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
* am335x: ddr_defs: Update EMIF parametersVaibhav Bedia2012-09-01-5/+5
| | | | | | | | | | | | | | | | | EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini2012-09-01-43/+35
| | | | | | | - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-01-3/+5
| | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Pass to config_ddr the type of memory that is connectedTom Rini2012-09-01-20/+31
| | | | | | | | | We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-01-61/+48
| | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework DDR2 EMIF initalization slightlyTom Rini2012-09-01-15/+2
| | | | | | | With the previous bugfix we now don't need to set two different REF_CTRL values and instead set the final value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Bugfix to config_sdram()Tom Rini2012-09-01-2/+1
| | | | | | | When we change SDRAM_CONFIG this triggers a refresh based on all of the parameters that we have programmed so we must do this last. Signed-off-by: Tom Rini <trini@ti.com>
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