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* fsl_lbc: add printout of LCRR and LBCR to local bus regsPaul Gortmaker2012-01-13-0/+4
| | | | | | | | It can be handy to have these in the output when trying to debug odd behaviour. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: Fix up local bus init to be frequency awarePaul Gortmaker2012-01-11-3/+35
| | | | | | | | | | | | | | | | | The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: enable support for hardware SPD errata workaroundPaul Gortmaker2012-01-11-7/+58
| | | | | | | | | | | | | | | | | | Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: relocate fixed ddr init code to ddr.c filePaul Gortmaker2012-01-11-44/+49
| | | | | | | | Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: Make enabling SPD RAM configuration workPaul Gortmaker2012-01-11-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: Fix LBC SDRAM initialization settingsPaul Gortmaker2012-01-11-20/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file for the board used during JTAG init sequence: LSDMR1 0x2863B727 /* PCHALL */ LSDMR2 0x0863B727 /* NORMAL */ LSDMR3 0x1863B727 /* MRW */ LSDMR4 0x4063B727 /* RFEN */ This differs from what was there already in that the RFEN is not bundled in all four steps implicitly, but issued once as the final step. The other difference seen when comparing vs. the register file init, is that since the memory is split across /CS3 and /CS4, the dummy writes need to go to 0xf000_0000 _and_ to 0xf400_0000. We also rewrite the final LBC SDRAM inits as macros, as there is no real need for them to be a local variable that is modified on the fly at runtime. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: enable ability to boot from alternate flashPaul Gortmaker2012-01-11-27/+142
| | | | | | | | | | | | | | | | | | | | | | | | | This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time. To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module. We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device. The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sbc8548: relocate 64MB user flash to sane boundaryPaul Gortmaker2012-01-11-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "SBC8548: fix address mask to allow 64M flash"Paul Gortmaker2012-01-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7. The commit "SBC8548: fix address mask to allow 64M flash" essentially made this change: * OR6: - * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 But this makes no sense, as section 13.3.1.2.1 in the MPC8548ERM v2 clearly indicates the masks: 1111_1111_1000_0000_0 8 Mbytes 1111_1100_0000_0000_0 64 Mbytes 1111_1000_0000_0000_0 128 Mbytes So the original value was correct, and the commit was invalid, causing a 128MB mapping for a 64MB flash device. The problem rears its head when trying to configure u-boot to have access to both flash, since the default memory map is: FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH By extending the mapping of the 64MB flash to 128MB, it now conflicts with the normal 8MB boot flash, causing issues. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBCPaul Gortmaker2012-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards were meaning to deploy this value: #define LCRR_DBYP 0x80000000 but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual. According to the documentation, LCRR_DBYP should be used as: PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less. So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows: Between 66 and 133, the DLL is enabled with an override workaround. In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROMKyle Moffett2012-01-11-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This EEPROM is hardware-write-protected and used to persist key information such as the serial number and MAC addresses even if the primary environment sector in NOR FLASH is overwritten. During manufacturing, the environment is initialized from Linux and then the key parameters copied to the EEPROM via U-Boot: env export -c -s 0x2000 $loadaddr serial# macaddr mac1addr mac2addr eeprom write $loadaddr 0x0000 0x2000 The chip is then locked via hardware for delivery. When doing a field U-Boot upgrade, the environment is erased and reset to the defaults to avoid problems with "hwconfig" changes, etc. After loading the new U-Boot image, the hardware data is reloaded: i2c dev 0 eeprom read $loadaddr 0x0000 0x2000 env import -c $loadaddr 0x2000 saveenv The first three commands are saved in the "restore_eeprom" variable for user convenience. (EG: "run restore_eeprom && saveenv") Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* eXMeritus HWW-1U-1A: Minor environment variable tweaksKyle Moffett2012-01-11-2/+5
| | | | | | | | | | | | | | | | | | | Most of the ethernet connections are internal links with specialized hardware and are not useful for "dhcp" or general-purpose networking; U-Boot should not be cycling through them. Force the primary external network interface in "ethprime" and disable the interface cycling with "ethrotate=no". Additionally, the environment variable "preboot" has its own config option and means something entirely different from what the HWW-1U-1A variable was intended for. Rename the board variable to "setbootargs" to avoid potential confusion. Finally, fix an incorrect address for the kernel in FLASH memory. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ARM: highbank: enable networking and pxeRob Herring2012-01-05-2/+28
| | | | | | | | This enables the XGMAC ethernet driver and networking related config options. Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* net: add Calxeda xgmac driverRob Herring2012-01-05-0/+558
| | | | | | | | | | This adds ethernet driver for Calxeda xgmac found on Highbank SOC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Fix: WARNING: __aligned(size) is preferred over __attribute__((aligned(size))) Signed-off-by: Wolfgang Denk <wd@denx.de>
* Correctly handle input files beginning with several newlinesDavid Wagner2012-01-05-5/+5
| | | | | | Also, fix some comments (minor) Signed-off-by: David Wagner <david.wagner@free-electrons.com>
* FAT: update the second FAT when writing a fileDonggeun Kim2012-01-05-0/+11
| | | | | | | | | | | | After susccessful write to the FAT partition, fsck program may print warning message due to different FAT, provided that the filesystem supports two FATs. This patch makes the second FAT to be same with the first one when writing a file. Signed-off-by: Donggeun Kim <dg77.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* usb_storage: Fix EHCI "out of buffer pointers" with CD-ROMKyle Moffett2012-01-05-20/+25
| | | | | | | | | | | | | | | | | When performing large bulk reads from a CD or DVD using the U-Boot usb_storage driver, it generates requests of up to 20 blocks at a time. With a standard 512-byte block size, that is 10240 bytes and within the limit of U-Boot's EHCI driver (maximum 5 pages at 4k per page). Unfortunately CD-ROM media has a 2048-byte blocksize, resulting in a maximum transfer size of 40960 bytes, which does not fit. Since the EHCI specification is impossibly obtuse and far beyond my comprehension, I chose to dynamically compute the limit based on the blocksize. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
* fs/fat: Improve error handlingKyle Moffett2012-01-05-4/+14
| | | | | | | | | | | | | | | | | | | | The FAT filesystem fails silently in inexplicable ways when given a filesystem with a block-size that does not match the device sector size. In theory this is not an unsupportable combination but requires a major rewrite of a lot of the filesystem. Until that occurs, the filesystem should detect that scenario and display a helpful error message. This scenario in particular occurred on a 512-byte blocksize FAT fs stored in an El-Torito boot volume on a CD-ROM (2048-byte sector size). Additionally, in many circumstances the ->block_read method will not return a negative number to indicate an error but instead return 0 to indicate the number of blocks successfully read (IE: None). The FAT filesystem should defensively check to ensure that it got all of the sectors that it asked for when reading. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
* fs/fat: Fix FAT detection to support non-DOS partition tablesKyle Moffett2012-01-05-63/+52
| | | | | | | | | | | | | | | | | | | The FAT filesystem code currently ends up requiring that the partition table be a DOS MBR, as it checks for the DOS 0x55 0xAA signature on the partition table (which may be Mac, EFI, ISO9660, etc) before actually computing the partition offset. This fixes support for accessing a FAT filesystem in an ISO9660 boot volume (El-Torito format) by reordering the filesystem checks and reading the 0x55 0xAA "DOS boot signature" and FAT/FAT32 magic number from the first sector of the partition instead of from sector 0. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Fix build warning: fat.c: In function 'fat_register_device': fat.c:66:15: warning: variable 'found_partition' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de>
* ext2: Cache line align indirection buffersSimon Glass2012-01-05-6/+12
| | | | | | | | Make ext2 use cache line aligned buffers for reading from the filesystem. This is needed when caches are enabled because unaligned cache invalidates are not safe. Signed-off-by: Simon Glass <sjg@chromium.org>
* tools/env: allow overwrite of ethaddr on defaultGrant Erickson2012-01-05-2/+11
| | | | | | | | | | | | | This patch allows the U-Boot user space companion utility, fw_setenv, to overwrite the 'ethaddr' key/value pair if the current value is set to a per-board-configured default. This change allows 'fw_setenv' to match the behavior of 'setenv' / 'env set' on the U-Boot command line. Signed-off-by: Grant Erickson <marathon96@gmail.com> Fixed excessive white space. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-01-05-134/+2687
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: tegra2: Optimize out-of-tree build for Ventana. tegra: Move boards over to use arch-level board UART function tegra: Add support for UART init in cpu board.c tegra: Add a function mux feature tegra: add clock_ll_start_uart() to enable UART prior to reloc tegra: Move clock_early_init() to arch_cpu_init() tegra: Move cpu_init_cp15() to arch_cpu_init() arm: Tegra: Fix Harmony and Ventana builds in u-boot-tegra/master tegra: Fix build error in plutux, medcom tegra2: Add Avionic Design Medcom support. tegra2: Add Avionic Design Plutux support. tegra2: Add common Avionic Design Tamonten support. tegra2: Move tegra2_mmc_init() prototype to public header. tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000. tegra2: Always build with USE_PRIVATE_LIBGCC=yes. tegra2: Plumb in SPI/UART switch code tegra2: spi: Support SPI / UART switch tegra2: Implement SPI / UART GPIO switch tegra2: Enable SPI environment on Seaboard tegra2: config: Enable SPI flash on Seaboard tegra2: spi: Add SPI driver for Tegra2 SOC tegra2: Add UARTB support tegra2: Tidy UART selection arm, davinci: Fix build warnings for cam_enc_4xx Devkit8000: Switch over to enable_gpmc_cs_config arm, davinci: Add support for generating AIS images to the Makefile mkimage: Fix variable length header support arm, da850evm: Add an SPL for SPI boot arm, davinci: Add SPL support for DA850 SoCs sf: Add spi_boot() to allow booting from SPI flash in an SPL spl: display_options.o is required for SPI flash support in SPL ARM: omap3: add support to Technexion twister board ARM: omap3: added common configuration for Technexion TAM3517 vision2: Fix checkpatch warning
| * tegra2: Optimize out-of-tree build for Ventana.Thierry Reding2011-12-24-2/+1
| | | | | | | | | | | | | | | | | | As proposed by Mike Frysinger, mkdir can take more than one argument. Instead of spawning two processes, create both the common and seaboard directories in one go. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Move boards over to use arch-level board UART functionSimon Glass2011-12-24-121/+5
| | | | | | | | | | | | | | | | | | Now that we can set up the UART in common tegra code, make the boards use it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Add support for UART init in cpu board.cSimon Glass2011-12-24-0/+81
| | | | | | | | | | | | | | | | | | | | We add a way of initialising the selected of UARTs prior to relocation. Boards can use the board_init_uart_f() instead of repeating this code themselves. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Add a function mux featureSimon Glass2011-12-24-1/+100
| | | | | | | | | | | | | | | | | | | | | | | | funcmux permits selection of config options for particular peripherals, such as the pins that are used for that peripheral, if there are several options. Add UART selection to start with. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add clock_ll_start_uart() to enable UART prior to relocSimon Glass2011-12-24-0/+25
| | | | | | | | | | | | | | | | | | | | Most boards will want to enable a UART early. This function provides that feature in Tegra architecture code so the code does not need to be copied on every board. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Move clock_early_init() to arch_cpu_init()Simon Glass2011-12-24-3/+3
| | | | | | | | | | | | | | | | | | The clock init is not board specific, so move it into the cpu code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Move cpu_init_cp15() to arch_cpu_init()Simon Glass2011-12-24-3/+4
| | | | | | | | | | | | | | | | | | This call is more of an architecture requirement than a board one, so move it there. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: Tegra: Fix Harmony and Ventana builds in u-boot-tegra/masterTom Warren2011-12-24-3/+4
| | | | | | | | | | | | | | Seaboard changes have removed the need for common/board.o in the Makefile. Propagate this change to the other Tegra2 builds. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Fix build error in plutux, medcomSimon Glass2011-12-24-0/+4
| | | | | | | | | | | | | | | | | | | | We need to define CONFIG_ENV_IS_NOWHERE to avoid this error: cmd_nvedit.c:69:3: error: #error Define one of CONFIG_ENV_IS_IN_... Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Add Avionic Design Medcom support.Thierry Reding2011-12-24-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Medcom is a 16:9 15" terminal that is used for patient infotainment in hospitals. Changes in v3: * Remove unused implementation of gpio_config_uart(). * Implement MMC/SD card detection. * Drop board_mmc_getcd() which is now implemented by common Tegra2 code. * Add MAINTAINERS entry. Changes in v2: * No longer override the default CONFIG_SYS_TEXT_BASE setting. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Add Avionic Design Plutux support.Thierry Reding2011-12-24-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Plutux is a set-top box device based on the Tamonten processor module. It can be connected to a display via an HDMI output. Changes in v3: * Remove unused implementation of gpio_config_uart(). * Implement MMC/SD card detection. * Drop board_mmc_getcd() which is now implemented by common Tegra2 code. * Add MAINTAINERS entry. Changes in v2: * No longer override the default CONFIG_SYS_TEXT_BASE setting. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Add common Avionic Design Tamonten support.Thierry Reding2011-12-24-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tamonten is an NVIDIA Tegra2-based SO-DIMM processor module that is derived from the Harmony reference design. Changes in v3: * Remove unused gpio_config_uart(). * Remove call to tegra2_start(). * Use new tegra2_mmc_init(). Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Move tegra2_mmc_init() prototype to public header.Thierry Reding2011-12-24-5/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of the Tegra2-based boards will need to call it, this commit exports it in the new public asm/arch/mmc.h header file to prevent each board from providing its own prototype. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000.Thierry Reding2011-12-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | NVIDIA's flashing tools assume that the bootloader is loaded at address 0x00108000. Instead of requiring non-standard builds of those tools which allow a load address of 0x00E08000, this commit just switches all Tegra2 boards to use the standard load address. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Always build with USE_PRIVATE_LIBGCC=yes.Thierry Reding2011-12-24-0/+2
| | | | | | | | | | | | | | | | | | | | The AVP on Tegra2 doesn't boot properly when U-Boot is linked against the GCC provided libgcc. To work around this, always build and link against a private libgcc for Tegra2-based boards. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Plumb in SPI/UART switch codeSimon Glass2011-12-24-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Seaboard the UART and SPI interfere with each other. This causes the UART to receive spurious zero bytes after SPI transactions and also means that SPI can corrupt a few output characters when it starts up if they are still in the UART buffer. This updates the board to use the SPI/UART switch to avoid the problem. For now this feature is turned off since it needs changes to the NS16550 UART to operate. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: spi: Support SPI / UART switchSimon Glass2011-12-24-0/+14
| | | | | | | | | | | | | | | | | | | | Add the SPI / UART switch logic into the Tegra2 SPI driver so that it can co-exist with the NS16550 UART. We need the ns16550.h header for NS16550_t for now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Implement SPI / UART GPIO switchSimon Glass2011-12-24-1/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra2 Seaboard has the unfortunate feature that SPI and the console UART are multiplexed on the same pins. We need to switch between one and the other during SPI and console activity. This new file implements a switch and keeps track of which peripheral owns the pins. It also flips over the controlling GPIO as needed Since we are adding a second file to board/nvidia/common, we create a proper Makefile there and remove the direct board.o include from board/nvidia/seaboard/Makefile Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Enable SPI environment on SeaboardSimon Glass2011-12-24-2/+13
| | | | | | | | | | | | | | This uses the SPI flash on Seaboard to store an 8KB environment. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: config: Enable SPI flash on SeaboardSimon Glass2011-12-24-0/+11
| | | | | | | | | | | | | | The Seaboard includes a Winbond 4MB flash part. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: spi: Add SPI driver for Tegra2 SOCTom Warren2011-12-24-0/+347
| | | | | | | | | | | | | | This driver supports SPI on Tegra2, running at 48MHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * tegra2: Add UARTB supportSimon Glass2011-12-24-0/+10
| | | | | | | | | | | | | | UARTB is used on some boards, so support it here. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Tidy UART selectionSimon Glass2011-12-24-23/+34
| | | | | | | | | | | | | | | | UART selection is done with a lot of #ifdefs. This cleans things up a little. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm, davinci: Fix build warnings for cam_enc_4xxChristian Riesch2011-12-24-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a build warning for the cam_enc_4xx board introduced by commit d6ec0c0dfc70447cf615ae80a952da81f73f16b4: spl.c:35:13: warning: 'gdata' defined but not used spl.c:36:13: warning: 'bdata' defined but not used Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de>
| * Devkit8000: Switch over to enable_gpmc_cs_configThomas Weber2011-12-24-7/+12
| | | | | | | | | | | | | | Use enable_gpmc_cs_config instead of local writing timing configuration for GPMC. Signed-off-by: Thomas Weber <weber@corscience.de>
| * arm, davinci: Add support for generating AIS images to the MakefileChristian Riesch2011-12-24-0/+14
| | | | | | | | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
| * mkimage: Fix variable length header supportChristian Riesch2011-12-24-48/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for variable length images like AIS image was introduced in commit f0662105b674a3874227316abf8536bebc9b5995. A parameter "-s" was also introduced to prohibit copying of the image file automatically in the main program. However, this parameter was implemented incorrectly and the image file was copied nevertheless. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * arm, da850evm: Add an SPL for SPI bootChristian Riesch2011-12-24-1/+172
| | | | | | | | | | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
generated by cgit v1.1 at 2024-11-09 20:24:11 +0000