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* Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2010-04-28-0/+28
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| * MX31: Added LCD support for QONG moduleStefano Babic2010-04-27-0/+28
| | | | | | | | | | | | | | Added support for LCD and splash image to the QONG module. The supported display is VBEST-VGG322403. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-04-28-35/+67
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| * mpc83xx: turn on icache in core initialization to improve u-boot boot timeKim Phillips2010-04-22-26/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before, MPC8349ITX boots u-boot in 4.3sec: column1 is elapsed time since first message column2 is elapsed time since previous message column3 is the message 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX 0.000 0.000: 0.000 0.000: Reset Status: 0.000 0.000: 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.032 0.000: Board: Freescale MPC8349E-mITX 0.032 0.000: UPMA: Configured for compact flash 0.032 0.000: I2C: ready 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 1.516 1.456: FLASH: 16 MB 2.641 1.125: PCI: Bus Dev VenId DevId Class Int 2.652 0.011: 00 10 1095 3114 0180 00 2.652 0.000: PCI: Bus Dev VenId DevId Class Int 2.652 0.000: In: serial 2.652 0.000: Out: serial 2.652 0.000: Err: serial 2.682 0.030: Board revision: 1.0 (PCF8475A) 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic 3.080 0.000: TSEC0, TSEC1 4.300 1.219: IDE: Bus 0: .** Timeout ** after, MPC8349ITX boots u-boot in 3.0sec: 0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX 0.010 0.000: 0.010 0.000: Reset Status: 0.010 0.000: 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.017 0.000: Board: Freescale MPC8349E-mITX 0.038 0.020: UPMA: Configured for compact flash 0.038 0.000: I2C: ready 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 0.260 0.222: FLASH: 16 MB 1.390 1.130: PCI: Bus Dev VenId DevId Class Int 1.390 0.000: 00 10 1095 3114 0180 00 1.390 0.000: PCI: Bus Dev VenId DevId Class Int 1.400 0.010: In: serial 1.400 0.000: Out: serial 1.400 0.000: Err: serial 1.400 0.000: Board revision: 1.0 (PCF8475A) 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic 1.832 0.000: TSEC0, TSEC1 3.038 1.205: IDE: Bus 0: .** Timeout ** also tested on these boards (albeit with a less accurate boottime measurement method): seconds: before after 8349MDS ~2.6 ~2.2 8360MDS ~2.8 ~2.6 8313RDB ~2.5 ~2.3 #nand boot 837xRDB ~3.1 ~2.3 also tested on an 8323ERDB. v2: also remove the delayed icache enablement assumption in arch ppc's board.c, and add a CONFIG_MPC83xx define in the ITX config file for consistency (even though it was already being defined in 83xx' config.mk). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: enable command line autocompletionKim Phillips2010-04-22-3/+17
| | | | | | | | | | | | because it's convenient. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: use "A" nomenclature only on mpc834x and mpc836x familiesKim Phillips2010-04-22-1/+3
| | | | | | | | | | | | | | | | | | marketing didn't extend their postpend-with-an-A naming strategy on rev.2's and higher beyond the first two 83xx families. This patch stops us from misreporting we're running e.g., on an MPC8313EA, when such a name doesn't exist. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clkRini van Zetten2010-04-22-5/+5
| | | | | | | | | | | | | | | | | | | | | | Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a platform define. This will enable all the 83xx platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. It's the same patch as commit 6b9ea08c5010eab5ad1056bc9bf033afb672d9cc for the ppc/85xx. Signed-off-by: Rini <rini@arvoo.nl> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2010-04-27-93/+1911
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| * | mpc5121: pdm360ng: add coprocessor POSTAnatolij Gustschin2010-04-24-0/+145
| | | | | | | | | | | | | | | | | | Adds coprocessor communication POST code Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc5121: add common post_word_load/store codeAnatolij Gustschin2010-04-24-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | Add common post_word_load/post_word_store routines for all mpc5121 boards. pdm360ng board POST support added by subsequent patch needs them. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc5121: add support for PDM360NG boardAnatolij Gustschin2010-04-24-6/+1307
| | | | | | | | | | | | | | | | | | | | | | | | PDM360NG is a MPC5121E based board by ifm ecomatic gmbh. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc5121: determine RAM size using get_ram_size()Anatolij Gustschin2010-04-24-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Configure CONFIG_SYS_MAX_RAM_SIZE address range in DDR Local Access Window and determine the RAM size. Fix DDR LAW afterwards using detected RAM size. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc512x: make MEM IO Control configuration a board config optionAnatolij Gustschin2010-04-24-5/+7
| | | | | | | | | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc5121: add PSC serial communication routinesAnatolij Gustschin2010-04-24-0/+94
| | | | | | | | | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | mpc512x: add multi serial PSC supportAnatolij Gustschin2010-04-24-81/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend mpc512x serial driver to support multiple PSC ports. Subsequent patches for PDM360NG board support make use of this functionality by defining CONFIG_SERIAL_MULTI in the board config file. Additionally the used PSC devices are specified by defining e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6. Support for PSC devices other than 1, 3, 4 and 6 is not added by this patch because these aren't used currently. In the future it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c. Additionally you have to add code for registering added devices in serial_initialize() in common/serial.c. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-04-27-62/+201
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| * | | ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQKumar Gala2010-04-26-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC83xx SERDES control is different from the other FSL PPC chips. For now lets split it out so we can standardize on interfaces for determining of a device on SERDES is configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flashLan Chunhe2010-04-26-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lan Chunhe <b25806@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx: clean up the io_sel for PCI express of P1022Dave Liu2010-04-26-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx/socrates: Remove NFS support to fit image size.Detlev Zundel2010-04-26-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes an overflow during the link phase. Signed-off-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx: Fix compile warningKumar Gala2010-04-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.c: In function 'checkcpu': cpu.c:47: warning: unused variable 'gur' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx: Convert cpu_init_f code to use out_be32 for LBC registersKumar Gala2010-04-26-18/+18
| | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl_sata: Move the snoop bit to another placeDave Liu2010-04-26-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For P1022 SATA host controller, the data snoop bit of DW3 in PRDT is moved to bit28. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl_sata: Add the workaround for errata SATA-A001Dave Liu2010-04-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After power on, the SATA host controller of P1022 Rev1 is configured in legacy mode instead of the expected enterprise mode. Software needs to clear bit[28] of HControl register to change to enterprise mode after bringing the host offline. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl-ddr: Add extra cycle to turnaround timesDave Liu2010-04-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an extra cycle turnaround time to read->write to ensure stability at high DDR frequencies. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl-ddr: add the macro for Rtt_Nom definitionDave Liu2010-04-26-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | add the macro definition for Rtt_Nom termination value for DDR3 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 definesKumar Gala2010-04-26-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Extend the GUTS memory mapDave Liu2010-04-26-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/p4080: Fix synchronous frequency calculationsSrikanth Srinivasan2010-04-26-21/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | ppc/85xx: Fixup PCI nodes for P1_P2_RDBKumar Gala2010-04-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we had ft_pci_board_setup it wasn't being called by ft_board_setup. Fix that so we actually update the device tree PCI nodes on P1_P2_RDB boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | | Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2010-04-27-8/+640
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| * | | nios2: add nios2-generic boardThomas Chou2010-04-24-0/+545
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a generic approach to port u-boot for nios2 boards. You may find the usage of this approach on the nioswiki, http://nioswiki.com/DasUBoot A fpga parameter file, which contains base address information and drivers declaration, is generated from Altera's hardware system description sopc file using tools. The example fpga parameter file is compatible with EP1C20, EP1S10 and EP1S40 boards. So these boards can be removed after this commit. Though epcs controller is removed to cut the dependency of altera_spi driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: fix no flash, add nand and mmc init in board.cThomas Chou2010-04-24-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes error when CONFIG_SYS_NO_FLASH. And adds nand flash and mmc initialization, which should go before env initialization. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: consolidate reset initializationThomas Chou2010-04-24-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Global interrupt should be disabled from the beginning. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | altera_jtag_uart: bypass when no jtag connectionThomas Chou2010-04-24-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an option to bypass output waiting when there is no jtag connection. This allows the jtag uart work similar to a serial uart, ie, boot even without connection. This option is enabled with CONFIG_ALTERA_JTAG_UART_BYPASS Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: add dma_alloc_coherentThomas Chou2010-04-24-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function return cache-line aligned allocation which is mapped to uncached io region. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: add 64 bits swab supportThomas Chou2010-04-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 64 bits swab support. Most 32 bits processors use this. We need 64 bits swab for UBI. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: add altera cf resetThomas Chou2010-04-24-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch toggles power to reset the cf card. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | nios2: allow link script overriding from boardsThomas Chou2010-04-24-1/+1
| |/ / | | | | | | | | | | | | | | | | | | This patch allow boards to override the default link script. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | | serial: struct serial_device: add uninit() entry for driversAnatolij Gustschin2010-04-24-0/+14
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subsequent patch extends mpc512x serial driver to support multiple PSC ports. The driver will provide an uninit() function to stop the serial controller and to disable the controller's clock. Adding uninit() entry to struct serial_device allows disabling the serial controller after usage of a stdio serial device. This patch adds uninit() entry to the struct serial_device and fixes initialization of this structure in the code accordingly. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcWolfgang Denk2010-04-24-2/+87
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| * | ppc/85xx: PIO Support for FSL eSDHC Controller DriverDipen Dudhat2010-04-23-2/+87
| |/ | | | | | | | | | | | | On some Freescale SoC Internal DMA of eSDHC controller has bug. So PIO Mode has been introduced to do data transfer using CPU. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-04-24-676/+313
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| * | ppc4xx: TLB init file cleanupStefan Roese2010-04-19-676/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2010-04-24-209/+174
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| * | | microblaze: Consolidate cache codeMichal Simek2010-04-16-44/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge cpu and lib cache code. Flush cache before disabling. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Flush cache before jumping to kernelMichal Simek2010-04-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is used max cache size on system which doesn't define cache size. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Support system with WB cacheMichal Simek2010-04-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WB cache use different instruction that WT cache but the major code is that same. That means that wdc.flush on system with WT cache do the same thing as before. You need newer toolchain with wdc.flush support. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Change initialization sequenceMichal Simek2010-04-16-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | env_relocation should be called first. Added stdio_init too. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Change cache report messagesMichal Simek2010-04-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | It is more accurate to show that caches are OFF instead of FAIL. Signed-off-by: Michal Simek <monstr@monstr.eu>
generated by cgit v1.1 at 2024-11-10 01:39:18 +0000