| Commit message (Collapse) | Author | Age | Lines |
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can print available cores (type: AHB Master, AHB Slave, APB Slave), their address ranges, IRQ number and version.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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fdt.c: In function 'ft_cpu_setup':
fdt.c:33: warning: implicit declaration of function 'do_fixup_by_prop_u32'
fdt.c:39: warning: implicit declaration of function 'do_fixup_by_compat_u32'
fdt.c:43: warning: implicit declaration of function 'fdt_fixup_ethernet'
fdt.c:45: warning: implicit declaration of function 'fdt_fixup_memory'
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The fdt set command was treating properties specified as <00> and <0011>
as byte streams, rather than as an array of cells. As we already have
syntax for expressing the desire for a stream of bytes ([ xx xx ...]),
we should use the <> syntax to describe arrays of cells, which are always
32-bits per element. If we imagine this likely (IMHO) scenario:
> fdt set /ethernet-phy@1 reg <1>
With the old code, this would create a bad fdt, since the reg cell would be
made to be one byte in length. But the cell must be 4 bytes, so this would
break mysteriously.
Also, the dts spec calls for constants inside the angle brackets (<>)
to conform to C constant standards as they pertain to base.
Take this scenario:
> fdt set /ethernet@f00 reg <0xe250000\ 0x1000>
The old fdt command would complain that it couldn't parse that. Or, if you
wanted to specify that a certain clock ran at 33 MHz, you'd be required to
do this:
> fdt set /mydev clock <1f78a40>
Whereas the new code will accept decimal numbers.
While I was in there, I extended the fdt command parser to handle property
strings which are split across multiple arguments:
> fdt set /ethernet@f00 interrupts < 33 2 34 2 36 2 >
> fdt p /ethernet@f00
ethernet@f00 {
interrupts = <0x21 0x2 0x22 0x2 0x24 0x2>;
};
Lastly, the fdt print code was rearranged slightly to print arrays of cells
if the length of the property is a multiple of 4 bytes, and to not print
leading zeros.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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finish off what commit 43ddd9c820fec44816188f53346b464e20b3142d,
"Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T"
started.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Stelian Pop <stelian@popies.net>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Support for booting from internal DataFlash, external DataFlash card
or NAND flash is available.
Signed-off-by: Stelian Pop <stelian@popies.net>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Adapt the existing AT91CAP9 code to the new headers and APIs.
Signed-off-by: Stelian Pop <stelian@popies.net>
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Replace AT91CAP9.h file with several splitted header files coming
from the Linux kernel.
This is part 2 of the replacement: more header imports and edits.
Signed-off-by: Stelian Pop <stelian@popies.net>
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Replace AT91CAP9.h file with several splitted header files coming
from the Linux kernel.
This is part 1 of the replacement: pristine header files import.
Signed-off-by: Stelian Pop <stelian@popies.net>
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AT91CAP9 and AT91SAM9 SoCs are very close hardware wise, so a
common infrastructure can be used. Let this infrastructure be
named after the AT91SAM9 family, and move the existing AT91CAP9
files to the new place.
Signed-off-by: Stelian Pop <stelian@popies.net>
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The timer on AT91CAP9/AT91SAM9 is supplied by the SoC, and not by
the board, so use timer_init() instead of interrupt_init().
Signed-off-by: Stelian Pop <stelian@popies.net>
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DataFlash partition information has become a mess. This patch
defines a single partition scheme for Atmel DataFlashes. This partition
scheme will be used by all AT91CAP9 and AT91SAM9 boards.
Signed-off-by: Stelian Pop <stelian@popies.net>
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Many Atmel boards have no "real" (NOR) flash on board, and rely only
on DataFlash and NAND memories. This patch enables CFG_NO_FLASH to
be present in a board configuration file, while still enabling flash
commands like 'flinfo', 'protect', etc.
Signed-off-by: Stelian Pop <stelian@popies.net>
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This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This
makes code use the register name from chip datasheets.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This
makes code use the register name from chip datasheets.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Add some missing ARM boards to MAKEALL. These build correctly,
unlike several of the boards already listed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch makes SPARC/LEON processors able to read and write
to the SMC91111 chip using the chip external I/O bus of the memory
controller. This patchs defines the standard in and out macros
expected by the SMC9111 driver.
To access that I/O bus one must set up the memory controller
(MCTRL or FTMCTRL) correctly. It is assumed that the user sets
up this correctly when the other MCTRL parameters are set up. It
can be set up from the board configuration header file.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This typo was introduced in commit 233a8bcd94997f3f345833a3b82e836222f2a206. I
actually applied the wrong patch.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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GRETH is an Ethernet 10/100 or 10/100/1000 MAC with out without
a debug link (EDCL). The GRETH core is documented in GRIP.pdf
available at www.gaisler.com.
If the GRETH has GigaBit support (GBIT, Scatter gather, checksum
offloading etc.) can be determined by a bit in the control register.
The GBIT MAC is supported by operating in GRTEH 10/100 legacy mode.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Provide common configuration in do_mii() to execute mii_init()
for all cpu architectures
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Added option CONFIG_BOOTP_DHCP_REQUEST_DELAY. This provides an optional
delay before sending "DHCP Request" in net/bootp.c. Required to overcome
interoperability problems with Windows Server 200x DHCP server when U-Boot
client responds too fast for server to handle.
Signed-off-by: Aras Vaichas <arasv@magtech.com.au>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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When the version_string function in start.S is not 4-byte align,
it will cause the compiler generates "unaligned opcodes detected
in executable segment". This issue affects all ColdFire CPUs.
By adding .align 4 after CONFIG_IDENT_STRING, it will pad 0's if
it is not aligned.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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This board never went into production
Signed-off-by: Zachary P. Landau <zachary.landau@labxtechnologies.com>
Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: Matthew Fettke <mfettke@videon-central.com>
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: Matthew Fettke <mfettke@videon-central.com>
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: Matt Wadel <Matt.Waddel@freescale.com>
Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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All of the duplicated code for Blackfin processors and boot modes have been
unified. After all, the core is the same for all processors, just the
peripheral set differs (which gets handled in the drivers).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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