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* sunxi: axp221: Make dcdc1 voltage configurableHans de Goede2015-01-14-1/+13
| | | | | | | | | | The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to safe battery, but not on all, make it configurable so that we can use the same settings as the original firmware on all boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usageHans de Goede2015-01-14-19/+14
| | | | | | | | | Some of the ldo-s of the axp221 are used in the same way on most boards, add comments to the Kconfig help text to reflect this, and give them defaults matching their typical usage. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp221: Add axp223 supportHans de Goede2015-01-14-26/+76
| | | | | | | | | The axp223 appears to be the same as the axp221, except that it uses the rsb to communicate rather then the p2wi. At least all the registers we use are 100% the same. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add support for the rsb (Reduced Serial Bus)Hans de Goede2015-01-14-1/+219
| | | | | | | | | | | | sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/Hans de Goede2015-01-14-10/+10
| | | | | | | | The p2wi interface is only available on sun6i, adjust the gpio pinmux and base address defines for it to reflect this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: sunxi: Fix misuse of gpio_direction_input()Axel Lin2015-01-14-3/+6
| | | | | | | | | | | | It does not make sense to make gpio_direction_input() return the gpio input status. The return value of gpio_direction_input() is inconsistent if CONFIG_DM_GPIO is defined. And we don't need to call gpio_direction_input() int sunxi_mmc_getcd(). Just init the gpio once in mmc_resource_init() is enough. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Align PSCI stack calculation to commentJan Kiszka2015-01-14-1/+1
| | | | | | | | 0x400 is true 1K. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add new board Merrii Hummingbird A31Chen-Yu Tsai2015-01-14-0/+28
| | | | | | | | | | The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add sunxi_get_sid helper functionHans de Goede2015-01-14-13/+31
| | | | | | | | | | On sun6i the SID is stored in the pmic, rather then in the SoC itself, add a helper function to abstract this away. This makes our MAC address generation code also work on sun6i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: axp221: Add axp221_get_sid functionHans de Goede2015-01-14-0/+33
| | | | | | | | For sun6i the SID is stored in the pmic, rather then in the SoC itself, add a function to retreive the sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mmc: Properly setup mod-clk and clock sampling phasesHans de Goede2015-01-14-36/+83
| | | | | | | | | | | | | | | | | | | | | | | The sunxi mmc controller has both an internal clock divider, as well as the divider in the mod0-clk for the mmc controller. The internal divider cannot be used, as it conflicts with the setting of clock sampling phases which is done in the mod0-clk, so it must be set to 0 (divide by 1). For some reason while the kernel has had this correct from day one, the u-boot sunxi mmc code has been using a fixed mod0-clk and setting its internal divider depending on the desired speed. This is something which we've inherited from the original Allwinner u-boot sources, but while this has been fixed in Allwinner's own u-boot code at least for the A23 and later upstream u-boot was still doing this wrong. This commit fixes this, thereby also fixing mmc support not working reliable on the A23 (which seems more sensitive to this) and possible also fixes some other sunxi mmc issues. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Update Colombus defconfig settingsHans de Goede2015-01-14-3/+10
| | | | | | | | | | | | | | The Colombus defconfig settings are missing a number of settings for recently added features, because we did not know exactly how things were hooked up. Maxime Ripard has run various tests to get us the necessary details, this commit updates the defconfig with this info. This commit also updates the dram clk and zq values with values verified by Maxime to be the ones used by the original firmware for this board. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add new CSQ_CS908 boardHans de Goede2015-01-14-1/+22
| | | | | | | | | | | | | The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND, rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG controller), ethernet, 3.5 mm jack with a/v out and hdmi out: http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html Note it has no sdcard slot and therefore can only be fel booted. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: dram: Do not try to initialize a second dram chan on A31sHans de Goede2015-01-14-7/+15
| | | | | | | | The A31s only has one dram channel, so do not bother with trying to initialize a second channel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add sunxi_get_ss_bonding_id() functionHans de Goede2015-01-14-2/+45
| | | | | | | | Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between the A31s and the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Make dram clk and zq value Kconfig optionsHans de Goede2015-01-14-7/+26
| | | | | | | | | | | | It turns out that there is a too large spread between boards to handle this with a default value, turn this into Kconfig options, and set the values the factory images are using for the Colombus and Mele_M9 boards. Note this changes the ZQ default when not overriden through defconfig from 120 to 123, as that is what most boards seem to actually use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-01-13-715/+1416
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| * x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.hBin Meng2015-01-13-1/+0
| | | | | | | | | | | | | | | | CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove it to avoid duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Update README.x86 for coreboot supportBin Meng2015-01-13-2/+37
| | | | | | | | | | | | | | | | Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Configure pci memory regionsBin Meng2015-01-13-2/+28
| | | | | | | | | | | | | | | | Configure coreboot pci memory regions so that pci device drivers could work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Wrap cros_ec initializationBin Meng2015-01-13-0/+2
| | | | | | | | | | | | | | | | cros_ec_board_init() should be called only when CONFIG_CROS_EC is enabled. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Make chromebook_link the default board for corebootBin Meng2015-01-13-223/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Remove include/configs/coreboot.hBin Meng2015-01-13-71/+1
| | | | | | | | | | | | | | | | Since we already swtiched to use the new mechanism for building U-Boot for coreboot, coreboot.h is no longer needed so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move CONFIG_SYS_CAR_xxx to KconfigBin Meng2015-01-13-2/+22
| | | | | | | | | | | | | | | | | | | | Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng2015-01-13-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | There are many places in the U-Boot source tree which refer to CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT that is currently defined in coreboot.h. Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch to board configuration file to build U-Boot later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurableBin Meng2015-01-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | In theory U-Boot built for coreboot is supposed to run as a payload to be loaded by coreboot on every board that coreboot supports. The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE which are hardcoded in board defconfig and Kconfig files. For better support of coreboot, we want to make these two options configurable so that we can easily change them during 'make menuconfig' so that the generated U-Boot image for coreboot is board configuration aware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selectedBin Meng2015-01-13-0/+2
| | | | | | | | | | | | | | | | When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip size is meaningless, hence hide it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng2015-01-13-4/+11
| | | | | | | | | | | | | | | | Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Allow a hardcoded TSC frequency provided by KconfigBin Meng2015-01-13-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By default U-Boot automatically calibrates TSC running frequency via MSR and PIT. The calibration may not work on every x86 processor, so a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to allow bypassing the calibration and assign a hardcoded TSC frequency CONFIG_TSC_FREQ_IN_MHZ. Normally the bypass should be turned on in a simulation environment like qemu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Set up timer base correctlyBin Meng2015-01-13-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value of base_time in coreboot's timestamp table as our timer base, otherwise TSC counter value will be used. Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, the value of base_time in the timestamp table is still zero, so we must exclude this case too (this is currently seen on booting coreboot in qemu). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-13-44/+14
| | | | | | | | | | | | | | | | | | | | | | These two are not worth having separate inline functions as they are really simple, so drop them. Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add an 'mtrr' command to list and adjust MTRRsSimon Glass2015-01-13-1/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed. Update the documentation to list some of the available commands. This does not support fixed MTRRs as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-13/+40
| | | | | | | | | | | | | | | | | | | | | | At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Disable CAR before relocation on platforms that need itSimon Glass2015-01-13-0/+8
| | | | | | | | | | | | | | For platforms with CAR we should disable it before relocation. Check if this function is available and call it if so. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-13-0/+46
| | | | | | | | | | | | | | Cache-as-RAM should be turned off when we relocate since we want to run from RAM. Add a function to perform this task. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Commit the current MTRRs before relocationSimon Glass2015-01-13-0/+8
| | | | | | | | | | | | | | | | Once we stop running from ROM we should set up the MTTRs to speed up execution. This is only needed for platforms that don't have an FSP. Also in the Coreboot case, the MTRRs are set up for us. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-13-0/+10
| | | | | | | | | | | | | | | | | | We should use MTRRs to speed up execution. Add a list of MTRR requests which will dealt with when we relocate and run from RAM. We set RAM as cacheable (with write-back) and registers as non-cacheable. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: board_f: Adjust x86 boot order for performanceSimon Glass2015-01-13-3/+5
| | | | | | | | | | | | | | | | For bare platforms we turn off ROM-caching before calling board_init_f_r() It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so that the copying happens before we turn off ROM-caching. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-13-0/+7
| | | | | | | | | | | | | | Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add support for MTRRsSimon Glass2015-01-13-101/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
| | | | | | | | | | | | | | | | | | | | This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Display vesa modes in hexSimon Glass2015-01-13-2/+2
| | | | | | | | | | | | | | | | The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up VESA mode numbersSimon Glass2015-01-13-4/+7
| | | | | | | | | | | | | | There are some bits which should be ignored when displaying the mode number. Make sure that they are not included in the mode that is displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Use cache, don't clear the display in video BIOSSimon Glass2015-01-13-3/+2
| | | | | | | | | | | | | | There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-13-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case. We could add a command to run the video BIOS later when needed, but this is not considered at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: video: Add debug option to time the BIOS copySimon Glass2015-01-13-0/+3
| | | | | | | | | | | | | | | | This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: pci: Don't return a vesa mode when there is not videoSimon Glass2015-01-13-1/+1
| | | | | | | | | | | | | | If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: video: Add a debug() to display the frame buffer addressSimon Glass2015-01-13-0/+1
| | | | | | | | | | | | Provide a way to display this address when booting. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Correct ifdtool microcode calculationSimon Glass2015-01-13-2/+2
| | | | | | | | | | | | | | | | This currently assumes that U-Boot resides at the start of ROM. Update it to remove this assumption. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop RAMTOP KconfigSimon Glass2015-01-13-12/+0
| | | | | | | | | | | | | | We don't need this in U-Boot since we calculate it based on available memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-09 09:50:59 +0000