| Commit message (Collapse) | Author | Age | Lines |
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i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR,
add support to this change for LPSR which needs to exit from
DDR retension mode.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
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Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the
pre-settings from boot rom. U-boot should re-init the USDHC not reply on the
value set by boot from.
On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021,
when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors.
Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too.
Signed-off-by: Ye.Li <B37916@freescale.com>
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change the imx7d arm2 nand rootfs partition index from 3 to 4 since the
weim nor was enabled by default and took the first mtd partition.
Signed-off-by: Han Xu <b45815@freescale.com>
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By Coverity check, the clk_set_rate function dereferences the clk pointer
without checking whether it is NULL. This may cause problem when clk is NULL.
Fix the problem by adding NULL check.
Signed-off-by: Ye.Li <B37916@freescale.com>
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According to the Coverity result, a unsigned int variable is used fo less-
than-zero comparison, the result is never true. Need to fix the variable
type to signed int.
Signed-off-by: Ye.Li <B37916@freescale.com>
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uboot will fail when loader zImage which is larger than 9M.
Increasing CONFIG_SYS_BOOTM_LEN from 8 MB to 16 MB is necessary to
support uncompressing images larger than 8 MB.
Signed-off-by: Zhang Sanshan <b51434@freescale.com>
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Android's tool chain enable the -mandroid at default.
This option will enable the -fpic, which cause uboot compilation
failure:
"
LD u-boot
u-boot contains unexpected relocations: R_ARM_ABS32
R_ARM_RELATIVE
"
In my testcase, arm-linux-androideabi-gcc-4.9 internally
enables '-fpic', so when compiling code, there will be
relocation entries using type R_ARM_GOT_BREL and .got
section. When linking all the built-in.o using ld, there
will be R_ARM_ABS32 relocation entry and .got section
in the final u-boot elf image. This can not be handled
by u-boot, since u-boot only expects R_ARM_RELATIVE
relocation entry.
arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic',
so there is not .got section and R_ARM_GOT_BREL in built-in.o.
And in the final u-boot elf image, all relocation entries are
R_ARM_RELATIVE.
we can pass '-fno-pic' to xxx-gcc to disable pic. whether
the toolchain internally enables or disables pic, '-fno-pic'
can work well.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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ret should not use unsigned integer. Should use signed interger to
compare against 0.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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birllo use gcc-4.9 to compile kernel, zImage is large then 8M.
set CONFIG_SYS_BOOTM_LEN to 16M
Signed-off-by: fang hui <b31070@freescale.com>
Conflicts:
include/configs/mx6ul_14x14_evk_brillo.h
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update will fail"
This reverts commit 24356fe059abbc9eae1b192f7af8a46f204a36f4.
Conflicts:
common/image-android.c
Conflicts:
common/image-android.c
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Windows DeviceIoControl SCSI_PASSTHROUGH is not stable when report media is
not ready.
Use dummy fat file to workaround this issue and avoid windows popup
format dialog.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
1.13<-1.12:
Change log:
1. Remove 20c4080
1.12<-1.10
Change log:
1. NoC register DDRCONF change to 0 which is compatible
for only CS0 is used on board
2. Change 2 values to compatible with our DDR aid script,
these two registers doesn’t have any effect on current system
tRPA = 0;
//this bit only used in DDR2 mode
tAOFPD/tAONPD=0x4;
//These register only works when MDPDC. SLOW_PD = 1 which is 0 in script
Test results:
One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed
60 hours memtester stress teset.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The fastboot.exe will get var partition-type:* firstly when "fastboot flash * *".
The uboot did not support get var partition-type: default.
This patch mask info the error when gat cat partition-type.
Signed-off-by: zhang sanshan <b51434@freescale.com>
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will fail
The ota update script will set selinux label with set_metadata when do nand ota update.
The root cause is set_metadata will fail if disable selinux in recovery mode.
This patch is a workaround which will enable selinux in recovery mode,
even if have disable selinux in commandline.
Signed-off-by: zhang sanshan <b51434@freescale.com>
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The ci_udc driver tries to use the ULPI interface for the USB OTG controller,
but this type is not supported by all i.MX6 and i.MX7 platforms. When setting to
ULPI, other platforms except the 6UL refuse the settings and keep default value.
But on 6UL, the PTW bit of PORTSC1 register which is documented as RO can change.
This cause the interface setting problem with USB PHY.
Fix the issue by removing the ULPI setting for i.MX6 and i.MX7. All will use default
UTMI setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Fixed the issue that mfgtool failed to download u-boot with plugin enabled.
The u-boot plugin common codes should not call rom___pu_irom_hwcnfg_setup
when using serial download mode.
rom___pu_irom_hwcnfg_setup will load the IVT2 image from boot media, but this
is invalid for USB serial download mode.
Signed-off-by: Ye.Li <B37916@freescale.com>
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According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN
standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC
'APS' mode in standby. we add a 25mV margin to cover the IR drop and
board tolerance, so the standby voltage of VDD_SOC_IN should be
setting to 1.075V.
Signed-off-by: Bai Ping <b51503@freescale.com>
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on i.MX6QP SDB board, the SW1A/B/C regulator is used by
VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage
setting for VDD_ARM_IN should be corresponding to SW2. So fix
the regulator mismatch issue on i.MX6QP SDB board.
Signed-off-by: Bai Ping <b51503@freescale.com>
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http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef
http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1
Main change: (SDB board ddr density is different)
1. tRFC is different with density, tXS/tXPR refers tRFC
Test Results:
2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The current 36M offset will conflict with NAND FCB firmware2 when the
nand chip block is 1MB size. This patch change it to 36M + 1M offset,
so the redundant u-boot at firmware2 will not be broken.
Signed-off-by: Ye.Li <B37916@freescale.com>
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ddr script update to 1.09:
http://compass.freescale.net/livelink/livelink?func=ll&objId=
234694528&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board.
arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board.
Changelog:
1. Optimize DQS duty cycle setting
2. Optimize ZQ PU/PD value
Test results:
2 ARD boards.
2 6QP-SDB boards.
1 6DP-SDB board.
All passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
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1. Default support SPI-NOR for imx6q/dl/solo sabresd board.
2. Fix bug for mx6soloxxx_spinor_defconfig. "nosmp" should be
\"nosmp\".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Same issue as ENGR00321137, commit 3695635.
GIS module need total 3M+3M+1.5M+1.5M=9M video memory.
and sys reserved 16M memory for malloc.
When gis module enabled, malloc may failed to allocate memory
for other modules, that may cause system hang.
Expand malloc pool to 32M.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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The previous 8M address for NAND env might conflict with other boot
parameters as the NAND block size increasing, change it to 36M to avoid
it.
Signed-off-by: Han Xu <b45815@freescale.com>
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The cod change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes).
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Signed-off-by: Han Xu <b45815@freescale.com>
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enlarge the maximum nand page size and oob size to
16k byte and 1280byte.
Signed-off-by: Han Xu <b45815@freescale.com>
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According to the latest datasheet(Rev. C Draft 1, 10/2015) of
i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and
add a 25mV margin to cover the IR drop and board tolerance.
So setting VDD_SOC voltage to 0.975V.
Signed-off-by: Bai Ping <b51503@freescale.com>
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IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc",
update it to DCD and plugin for i.MX6UL 14x14 EVK board.
Updated items:
Removed:
0x020c4084
0x021B0858
Value changed:
0x020E027C
0x020E0280
0x021B0008
0x021B000C
0x021B0010
0x021B0018
0x021B08C0
The script versions of EVK board and Validation Board from the following link:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj
Action=browse&viewType=1
Test Results:
Two boards passed overnight memtester stress test.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The PST bit can't be set too small which will cause performance drop.
Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2
commit e1ca547d198dde94c4d8278c99499ec2d2008880
Signed-off-by: Ye.Li <B37916@freescale.com>
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The actual memory size is 256MB not 512MB, otherwise it has a wrap
problem in memory and will cause memtester failed.
Signed-off-by: Ye.Li <B37916@freescale.com>
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enable bank interleave feature to improve the performance
downloaded from
http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1
Before:
$ /opt/fsl-samples/g2d/g2d_test
Width 1920, Height 1088, Format RGBA, Bpp 32
---------------- g2d blit performance ----------------
g2d blit time 15566us, 64fps, 134Mpixel/s ........
g2d blending time 20672us, 48fps, 101Mpixel/s ........
g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........
---------------- g2d clear performance ----------------
g2d clear time 8433us, 118fps, 247Mpixel/s ........
---------------- g2d rotation performance ----------------
90 rotation time 15366us, 65fps, 135Mpixel/s ........
180 rotation time 15374us, 65fps, 135Mpixel/s ........
270 rotation time 15373us, 65fps, 135Mpixel/s ........
g2d flip-h time 15373us, 65fps, 135Mpixel/s ........
g2d flip-v time 15372us, 65fps, 135Mpixel/s ........
...
After:
$ /opt/fsl-samples/g2d/g2d_test
Width 1920, Height 1088, Format RGBA, Bpp 32
---------------- g2d blit performance ----------------
g2d blit time 2810us, 355fps, 743Mpixel/s ........
g2d blending time 4025us, 248fps, 518Mpixel/s ........
g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........
---------------- g2d clear performance ----------------
g2d clear time 1846us, 541fps, 1131Mpixel/s ........
---------------- g2d rotation performance ----------------
90 rotation time 5234us, 191fps, 399Mpixel/s ........
180 rotation time 3176us, 314fps, 657Mpixel/s ........
270 rotation time 5248us, 190fps, 398Mpixel/s ........
g2d flip-h time 2765us, 361fps, 755Mpixel/s ........
g2d flip-v time 3179us, 314fps, 657Mpixel/s ........
...
Signed-off-by: Robby Cai <r63905@freescale.com>
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Add android and sata defconfig file.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since the mx6ul 9x9 evk has different DDR size with 14x14 evk, change
to use the half of PHYS_SDRAM_SIZE for mtest end.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The DDR initialization in plugin needs to update conformably with DCD.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This piece of code is for mx7, we should not use
do_mx6_showclocks.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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MMDC auto power saving timer can NOT be too small,
as enter/exit auto self-refresh mode too frequently
may introduce too many latency for MMDC access,
set it to 0x10, same as previous value on i.MX6.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add i.MX6QP SabreSD board support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Need to check fuse bit 25 of bank 0 word 4 before initialize bee.
The bit: 0 means bee enabled, 1 means bee disabled.
If disabled, continuing initialize bee will cause system hang, so
need to check this bit before initialize bee.
Add macro to enable BEE in header file, default disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We meet reset failure on mx6ul 9x9 evk. The internal reset logic between MMDC and
functional modules seems relate with the issue.
Turn off the LCDIF to stop DDR access before reset to avoid this possible internal
reset problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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The lpddr2 memsize of mx6ul_9x9_evk is 256MB, not 512M, so
the CS0_END should be 0x47, but not 0x4F.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Disable PFuze3000 low power mode during standby mode, otherwise,
if the power consumption exceed the threshold, PFuze will reboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add new build target: mx6ul_9x9_evk_qspi1_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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Updated items:
memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001
This is just enable when LPDDR4 is enabled .
memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046
T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45)
memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083
PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81
memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000
DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68
memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004
DEV_ZQINIT_X32 . Should be 16 clocks
memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109
T_FAW=(40ns*528Mhz)/2)=11
memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d
tXPDLL=24ns*528Mhz=13clocks
File:
MX7D_EVK_DDR3_1GB_32bit.ds
Test result:
3 boards pass 2 days stress test.
Signed-off-by: Ye.Li <B37916@freescale.com>
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i.MX6UL-9x9-EVK board has PFUZE3000, so enable LDO
bypass support for this board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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CONFIG_FASTBOOT is not used, since we have CONFIG_FSL_FASTBOOT and
CONFIG_CMD_FASTBOOT for fastboot. "drivers/fastboot" can be discarded.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine
generates is empty. This causes HAB to complain that the command is invalid.
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x0c 0x41 0x33 0x06 0xc0 0x00
0xcc 0x00 0x04 0x04
To fix this set the DCD pointer in the IVT to NULL in this case. The DCD header
itself is still needed for detect_imximage_version() to determine the image
version.
Conflicts:
tools/imximage.c
cherry-picked from
http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=873bf926bfbb0a667158261813115fa6819661b7
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Stefano Babic <sbabic@denx.de>
(cherry picked from commit 873bf926bfbb0a667158261813115fa6819661b7)
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This mx7d 19x19 lpddr2 arm2 board is based on 19x19 lpddr3 arm2 board
with DDR changed to 512M LPDDR2. We added DDR script for LPDDR2 and
a new u-boot build target: mx7d_19x19_lpddr2_arm2_config
LPDDR2 script source: lpddr2_0_1.ds
Signed-off-by: Ye.Li <B37916@freescale.com>
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