| Commit message (Collapse) | Author | Age | Lines |
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If CONFIG_MMC_SDHCI_IO_ACCESSORS is defined, the following warning would
shows up:
include/sdhci.h:224: warning: 'struct sdhci_host' declared inside
parameter list
include/sdhci.h:224: warning: its scope is only this definition or
declaration, which is probably not what you want
include/sdhci.h:225: warning: 'struct sdhci_host' declared inside
parameter list
include/sdhci.h:226: warning: 'struct sdhci_host' declared inside
parameter list
include/sdhci.h:227: warning: 'struct sdhci_host' declared inside
parameter list
include/sdhci.h:228: warning: 'struct sdhci_host' declared inside
parameter list
include/sdhci.h:229: warning: 'struct sdhci_host' declared inside
parameter list
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Only flush the memory range needed.
Signed-off-by: Lei Wen <leiwen@marvell.com>
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As per JEDEC document JESD84-A441 (page 105) response for CMD7
(MMC_CMD_SELECT_CARD) response should be R1 instead of R1b. In uboot we
never take MMC to disconnected state and on powerup its always ideal
state which later goes to stand-by state.
from document footnote:
R1 while selecting from Stand-By State to Transfer State; R1b while
selecting from Disconnected State to Programming State.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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For we don't know mmc bus width from reading registers, the only way
to check is to test.
Current compare offset is:
EXT_CSD_PARTITIONING_SUPPORT
EXT_CSD_ERASE_GROUP_DEF
EXT_CSD_REV
EXT_CSD_HC_ERASE_GRP_SIZE
EXT_CSD_SEC_CNT
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Previous magic number is hard to parse its meaning, change it to
respective macro definition
Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: WOlfgang Denk <wd@denx.de>
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Marvell 88SV331xV5 platform's sdhci host control is not very standard
with the spec in the 8bit handling. It need to set its private register
to switch to the 8bit mode which is not included in the standard sdhci
registers.
This patch mainly hacks the writeb method, and set its private register
if it find the driver is going to switch to the 8bit mode.
Signed-off-by: Lei Wen <leiwen@marvell.com>
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For some controller it has dynamic clock gating, and only toggle out clk
when the first cmd0 send out, while some card strictly obey the 74
clocks rule, the interval may not be sufficient between the cmd0 and
this cmd8, retry to fulfil the clock requirement.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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As a part of the manufacturing process for some of our custom hardware,
we are programming the EEPROMs attached to our Intel 82571EB controllers
from software using U-Boot and Linux.
This code provides several conditionally-compiled features to assist in
our manufacturing process:
CONFIG_CMD_E1000:
This is a basic "e1000" command which allows querying the controller
and (if other config options are set) performing EEPROM programming.
In particular, with CONFIG_E1000_SPI this allows you to display a
hex-dump of the EEPROM, copy to/from main memory, and verify/update
the software checksum.
CONFIG_E1000_SPI_GENERIC:
Build a generic SPI driver providing the standard U-Boot SPI driver
interface. This allows commands such as "sspi" to access the bus
attached to the E1000 controller. Additionally, some E1000 chipsets
can support user data in a reserved space in the E1000 EEPROM which
could be used for U-Boot environment storage.
CONFIG_E1000_SPI:
The core SPI access code used by the above interfaces.
For example, the following commands allow you to program the EEPROM from
a USB device (assumes CONFIG_E1000_SPI and CONFIG_CMD_E1000 are enabled):
usb start
fatload usb 0 $loadaddr 82571EB_No_Mgmt_Discrete-LOM.bin
e1000 0 spi program $loadaddr 0 1024
e1000 0 spi checksum update
Please keep in mind that the Intel-provided .eep files are organized as
16-bit words. When converting them to binary form for programming you
must byteswap each 16-bit word so that it is in little-endian form.
This means that when reading and writing words to the SPI EEPROM, the
bit ordering for each word looks like this on the wire:
Time >>>
------------------------------------------------------------------
... [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8], ...
------------------------------------------------------------------
(MSB is 15, LSB is 0).
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
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A followup patch will be adding a configurable feature to enable
programming of E1000 EEPROMs from the command line or via the generic
U-Boot SPI interface.
In order for it to work it needs access to certain E1000-internal
functions, so export those in the e1000.h header file.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
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As an aide to debugging, we should print out the expected value of the
EEPROM checksum in addition to just saying that it is wrong.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
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By allocating the e1000 device structures much earlier, we can easily
generate better error messages and siginficantly clean things up.
The only user-visable change (aside from reworded error messages) is
that a detected e1000 device which fails to initialize due to software
or hardware error will still be allocated a device number.
As one example, consider a system with 2 e1000 PCI devices where the
first controller has a corrupted EEPROM. Using the old code the
second controller would be "e1000#0", while with this change it would be
"e1000#1".
This change should hopefully make such EEPROM errors much more
straightforward to handle correctly in boot scripts and the like.
It is also necessary for a followup patch which allows SPI programming
of an e1000 controller's EEPROM even if the checksum is invalid.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
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Consolidate the test for a dual-port NIC to one location for easy
modification, then fix support for the dual-port 82571.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
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Fix to cast an integer to a pointer using uintptr_t.
Signed-off-by: Simon Glass <sjg@chromium.org>
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* 'master' of git://git.denx.de/u-boot-arm:
ARM: Add Calxeda Highbank platform
dkb: make mmc command as default enabled
Marvell: dkb: add mmc support
ARM: pantheon: add mmc definition
davinci: remove config.mk file from the sources
ARM:AM33XX: Add support for TI AM335X EVM
ARM:AM33XX: Added timer support
ARM:AM33XX: Add emif/ddr support
ARM:AM33XX: Add clock definitions
ARM:AM33XX: Added support for AM33xx
omap3/emif4: fix registers definition
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
davinci: emac: add support for more than 1 PHYs
davinci: emac: add new features to autonegotiate for EMAC
da850evm: Move LPSC configuration to board_early_init_f()
omap4_panda: Build in cmd_gpio support on panda
omap: Don't use gpio_free to change direction to input
mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
OMAP3: overo : Add environment variable optargs to bootargs
OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
OMAP3: overo : Use ttyO2 instead of ttyS2.
da830: add support for NAND boot mode
dm36x: revert cache disable patch
dm644X: revert cache disable patch
devkit8000: Add malloc space
omap: spl: fix build break due to changes in FAT
OMAP3 SPL: Provide weak omap_rev_string
omap: beagle: Use ubifs instead of jffs2 for nand boot
omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
omap: overo: Configure mux for gpio10
SPL: Add DMA library
omap3: Add interface for omap3 DMA
omap3: Add DMA register accessors
omap3: Add Base register for DMA
arm, davinci: add missing LSPC define for MMC/SD1
U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
DaVinci: correct MDSTAT.STATE mask
omap4: splitting padconfs into common, 4430 and 4460
omap4: adding revision detection for 4460 ES1.1
omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
gplug: fixed build error as a result of code cleanup patch
kirkwood_spi: add dummy spi_init()
gpio: mvmfp: reduce include platform file
ARM: orion5x: reduce dependence of including platform file
serial: reduce include platform file for marvell chip
ARM: kirkwood: reduce dependence of including platform file
ARM: armada100: reduce dependence of including platform file
ARM: pantheon: reduce dependence of including platform file
Armada100: Add env storage support for Marvell gplugD
Armada100: Add SPI flash support for Marvell gplugD
Armada100: Add SPI support for Marvell gplugD
SPI: Add SPI driver support for Marvell Armada100
dreamplug: initial board support.
imx: fix coding style
misc: pmic: drop old Freescale's pmic driver
MX31: mx31pdk: use new pmic driver
MX31: mx31ads: use new pmic driver
MX31: mx31_litekit: use new pmic driver
MX5: mx53evk: use new pmic driver
MX5: mx51evk: use new pmic driver
MX35: mx35pdk: use new pmic driver
misc: pmic: addI2C support to pmic_fsl driver
misc: pmic: use I2C_SET_BUS in pmic I2C
MX5: efikamx/efikasb: use new pmic driver
MX3: qong: use new pmic driver
RTC: Switch mc13783 to generic pmic code
MX5: vision2: use new pmic driver
misc: pmic: Freescale PMIC switches to generic PMIC driver
misc:pmic:samsung Enable PMIC driver at GONI target
misc:pmic:max8998 MAX8998 support at a new PMIC driver.
misc:pmic:core New generic PMIC driver
mx31pdk: Remove unneeded config
mx31: provide readable WEIM CS accessor
MX51: vision2: Set global macros
I2C: Add i2c_get/set_speed() to mxc_i2c.c
ARM: Update mach-types
devkit8000: Add config to enable SPL MMC boot
devkit8000: protect board_mmc_init
arm, post: add missing post_time_ms for arm
cosmetic, post: Codingstyle cleanup
arm, logbuffer: make it compileclean
tegra2: Enable MMC for Seaboard
tegra2: Add more pinmux functions
tegra2: Rename PIN_ to PINGRP_
tegra2: Add more clock functions
tegra2: Clean up board code a little
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
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Add basic support for Calxeda Highbank platform. Only minimal support with
serial and SATA are included.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
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Signed-off-by: Lei Wen <leiwen@marvell.com>
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Signed-off-by: Lei Wen <leiwen@marvell.com>
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Signed-off-by: Lei Wen <leiwen@marvell.com>
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To compile TI Davinci SoC support the identical config.mk file from
the cpu directory shall be used.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds basic support for booting the board.
This patch adds support for the UART necessary to
get to the u-boot prompt.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds timer support for AM33xx platform.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds AM33xx emif/ddr support along with board specific
defines.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds basic clock definition of am33xx SoC.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds basic support for AM33xx which is based on ARMV7
Cortex A8 CPU.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Fix EMIF4 registers definition.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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remove macro CONFIG_EMAC_MDIO_PHY_NUM and depending macro EMAC_MDIO_PHY_NUM
as they are no longer needed with the support for more than 1 PHYs in davinci
emac driver.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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add support for more than 1 PHYs. Many of the davinci platforms have more
than 1 PHYs on thier board. This patch extends support in davinci emac
driver for upto 3 PHYs.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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add more features like DUPLEX, 100MB link speed etc to auto negotiate
in EMAC driver. EMAC controller autonegotiates for these features with
PHYs which are on the board.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Since commit f1d2b313c9eb6808d30c16a9eb5251240452a56c the serial
port of the da850evm is accessed before the UART2 peripheral of
the SoC is powered on in the function board_init() in
board/davinci/da8xxevm/da850evm.c.
When u-boot is used in conjunction with the UBL (user boot loader, see
doc/README.davinci) on this board, the UART2 peripheral is already
turned on by UBL at the time u-boot is started. Hence, the wrong
initialization sequence is not noticed by most users. However, if UBL is not
used, u-boot must power on the peripheral before using it.
This patch adds a board_early_init_f() function for the LPSC
configuration to the da850evm board configuration.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Enable the gpio command
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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gpio_free() should not have the side effect of setting the line to input since this prevents the gpio command from being able to set a line as output.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Not all omap families define OMAP_HSMMC[23]_BASE so condition those
cases in omap_mmc_init().
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This allows the user can easily add extra kernel arguments. Very helpful
for reserving memory for the DSP without rewriting the entire kernel
argument line.
Signed-off-by: Philip Balister <philip@opensdr.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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By moving the CS4 configuration into the board specific configuration, it
is left free for custom carrier boards. The USRP-E1XX series uses
CS4 to control access to an FPGA, so without this patch the device driver
cannot claim CS4.
Signed-off-by: Philip Balister <philip@opensdr.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Starting with kernel 2.6.37, the serial ports on the OMAP3 are called
ttyOX, not ttySX.
Signed-off-by: Philip Balister <philip@opensdr.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Add support for enabling NAND boot mode in configuration file and
add correspanding pinmux support, nand initialize function in board file.
The size required for environment variables not more than 10KB
the CONFIG_ENV_SIZE is set to 10KB from (512 << 10).
Acked-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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revert commit 98c19aff9524e1d0dd6bf39bf7bde5644f121feb as the
disabling of cache need not be done explicitly. Subsequent
patches to new cache management framework has fixed it.
EMAC issue with cache coherency still exists when cahces are
enabled.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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revert commit 913a39e9aa4d935948d41cd727d53f5878414a77 as the
disabling of cache need not be done explicitly. Subsequent
patches to new cache management framework has fixed it.
EMAC issue with cache coherency still exists when cahces are
enabled.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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With malloc support being a new requirement for all ARM SPL
implementations, define a small area for use on devkit8000.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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FAT library now uses malloc() and free(). But SPL doesn't
have heap until now. Setup a heap in SDRAM to fix this issue.
However this increases SPL footprint beyond the available SRAM
budget. So, compile out some fancy features in the SDARM init
bring back footprint under control
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Wolfgang Denk <wd@denx.de>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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We add an weak version of omap_rev_string in omap-common/spl.c
and while at it drop the omap3 version. Move the prototype over
to <asm/omap_common.h> with the other SPL functions.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Koen Kooi <k-kooi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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The level shifters used on the Caspa camera module have a 4k output
impedance. Combined with the 100uA pull-up resistors in the OMAP3,
this raises the ground level to 400mV. Adding crosstalk between the
pixel clock and the HS/VS signals on the flat cable (a ground line in
between would have been nice), logic 0 levels can raise up to 650mV.
This exceeds the camera input pins VIL maximum voltage. This change
suggested-by Laurent Pinchart
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This pad was previously configured for sysclkout_1. This patch changes
the configuration to gpio_10 to reduce radiated noise from the 26Mhz
clock, as well as make the pin more generally useful.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding a DMA library to the SPL. It is used if CONFIG_SPL_DMA_SUPPORT is
defined.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adds an interface to use the OMAP3 DMA.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the register definitions for omap3 DMA controller to cpu.h
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the base register address of OMAP3 DMA controller.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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