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* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-13-6/+2379
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| * mx25pdk: Align the environment with other FSL boardsFabio Estevam2014-03-12-5/+98
| | | | | | | | | | | | | | | | | | | | | | Allow the boot of a device tree mainline kernel by aligning the environment variables with other FSL boards. Tested NFS boot of a dt 3.14-rc5 kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * ventana: Add Gateworks Ventana family supportTim Harvey2014-03-12-0/+2143
| | | | | | | | | | | | | | | | | | Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-03-05-82870/+36589
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| * | fb: Add a prototype for board_video_skip()Fabio Estevam2014-03-05-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a prototype for board_video_skip() in order to fix the following sparse warning: wandboard.c:227:5: warning: symbol 'board_video_skip' was not declared. Should it be static? Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | wandboard: Include <input.h>Fabio Estevam2014-03-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Include <input.h> in order to fix the following sparse warning: wandboard.c:278:5: warning: symbol 'overwrite_console' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | wandboard: Fix sparse warningFabio Estevam2014-03-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a prototype for board_phy_config() to fix the following sparse warning: wandboard.c:200:5: warning: symbol 'board_phy_config' was not declared. Should it be static? Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mmc: Add a prototype for board_mmc_init()Fabio Estevam2014-03-05-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following sparse warning: wandboard.c:137:5: warning: symbol 'board_mmc_init' was not declared. Should it be static? Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | wandboard: Staticize usdhc1_padsFabio Estevam2014-03-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: wandboard.c:58:22: warning: symbol 'usdhc1_pads' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | power: add PFUZE100 PMIC driverTim Harvey2014-03-05-0/+129
| | | | | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | board/BuR/kwb: fix usage of 'i2c_set_bus_speed'Hannes Petermaier2014-03-12-2/+2
| | | | | | | | | | | | | | | | | | - fix: return-value of 'i2c_set_bus_speed' was interpreted wrong Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* | | arm: am335x: DXR2: Move unconditional LAN9303 reset into commandStefan Roese2014-03-12-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The switch HW reset results in a disconnection of the switch port daisy- chain for a few seconds. This is not desired in the normal field use case. So lets remove this switch reset from the normal bootup sequence and move it into a board specific command. This way it can be executed in the development environment when really needed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com>
* | | drivers: net: cpsw: init phy with gigabit featuresIlya Ledvich2014-03-12-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | CPSW ia a gigabit device. Use the PHY_GBIT_FEATURES macro to determine phy supported features. Tested on cm_t335. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
* | | arm: omap: cm_t35: Fix: Re-add GPMC_NAND_ECC_LP_x8_LAYOUTStefan Roese2014-03-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch a7e36fc9 (mtd: nand: omap: remove unused #defines from common omap_gpmc.h) removed some MTD related defines. Including GPMC_NAND_ECC_LP_x8_LAYOUT. But this define is also needed for the memory controller configuration (only the x8 defines are needed, the x16 defines are the default). Without it the NAND subsystem is not configured correctly and booting into U-Boot does not work. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* | | am335x_evm: Remove SPI SPL from NOR support targetTom Rini2014-03-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using the am335x_evm_nor target one is generally expecting to be used in an environment when you want to program the NOR and not a "deployment" type target. In addition this only supports the Beaglebone White with the memory cape and NOR module installed, which precludes the presence of SPI flash. Drop SPI as we were getting close to the binary limit in some cases and slightly over with other toolchains. Signed-off-by: Tom Rini <trini@ti.com>
* | | drivers/spi/omap3: Bug fix of premature write transfer completionVasili Galka2014-03-12-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The logic determining SPI "write" transfer completion was faulty. At certain conditions (e.g. slow SPI clock freq) the transfers were interrupted before completion. Both EOT and TXS flags of channel status registeer shall be checked to ensure that all data was transferred. Tested on AM3359 chip. Signed-off-by: Vasili Galka <vasili@visionmap.com>
* | | am33xx: Rework #ifdef's around s_init for clarityTom Rini2014-03-12-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The s_init function is only called on SPL or XIP cases, so lets only build it for them. This makes the #if logic within the function a bit clearer as to when we are or are not calling things, and makes it easier to see that for example preloader_console_init isn't ever called in the non-XIP full U-Boot case. Signed-off-by: Tom Rini <trini@ti.com>
* | | Prepare v2014.04-rc2Tom Rini2014-03-10-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-10-91/+983
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| * | | arm: atmel: sama5d3: add nand spl boot supportBo Shen2014-03-09-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND SPL boot support with hardware PMECC. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | mtd: nand: atmel: prepare for nand spl boot supportBo Shen2014-03-09-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | arm: atmel: sama5d3: add spi spl boot supportBo Shen2014-03-09-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI SPL boot support for sama5d3xek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: atmel: add sama5d3 Xplained board supportBo Shen2014-03-09-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC. Now it supports boot from NAND flash and SD/MMC card. Features support: - NAND flash - SD/MMC card - Two USB hosts - Ethernet (one GMAC, one EMAC) Signed-off-by: Bo Shen <voice.shen@atmel.com> [reorder boards.cfg] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | at91 gpio: fix typo in compatibility macroAndreas Henriksson2014-03-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's called _pio_ in the version that was added to git. Apparently it got renamed without updating the macros before it was applied, c.f. http://u-boot.10912.n7.nabble.com/U-Boot-PATCH-3-9-V3-add-a-new-AT91-GPIO-driver-td75922.html Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | at91sam9263ek: add mmc supportAndreas Henriksson2014-03-09-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for using the Atmel MCI driver on at91sam9263ek. This change is modeled after the existing at91sam9260ek support. Please note that this hooks up slot1 (MCI1) for SD. Not both. Tested with at91bootstrap and u-boot on dataflash in slot 0 and fat-formatted 8GB SDHC in slot 1 on first revision at91sam9263ek (which must use dataflash in slot0 to boot). CONFIG_ATMEL_MCI_PORTB not tested. Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> [remove empty line] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-07-51/+95
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| | * | | ARM: tegra: implement bootcmd_pxeStephen Warren2014-03-05-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This retrieves a PXE config file over the network, and executes it. This allows an extlinux config file to be retrieved over the network and executed, whereas the existing bootcmd_dhcp retrieves a U-Boot script. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: rework boot scriptsStephen Warren2014-03-05-9/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the common Tegra boot scripts in the default environment to a) Make use of the new "test -e" shell command to avoid some error messages. b) Allow booting using the sysboot command and extlinux.conf. This allows easy creation of boot menus, and provides a simple interface for distros to parameterize/configure the boot process. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: convert tegra to use distro defaultsStephen Warren2014-03-05-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify all Tegra boards to include the "distro defaults" header, so that all the config options distros expect are enabled. Remove any #defines that enable the same options from the Tegra files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTSStephen Warren2014-03-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's EHCI controllers only have a single PORTSC register. Configure U-Boot to know this. This prevents e.g. ehci_shutdown() from touching non-existent registers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: simplify halt_avp()Stephen Warren2014-03-05-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to completely halt the AVP processor, we should simply write FLOW_MODE_STOP without any extra options that allow wakeup. Amend the code to do this. I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by interrupts. We don't want this; if later SW wishes to use the AVP, it should be reset and booted from scratch. Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly different definition starting with Tegra114, so the values we're writing don't entirely make sense there anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124Stephen Warren2014-03-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 moved the CSITE block's base address. Fix U-Boot to use the correct address. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: fix pmc_pwrgate_timer_mult register definitionStephen Warren2014-03-05-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register pmc_pwrgate_timer_mult has a different layout on Tegra114 and Tegra124. Reflect this in pmc.h. Also, simply write the whole of the register in start_cpu() rather than doing a read-modify-write; the register is simple enough that the code can easily construct the entire desired value. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: move CONFIG_TEGRAnnStephen Warren2014-03-05-20/+8
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize some definitions, since some modules moved between generations. Move the definition of CONFIG_TEGRAnn to a header that's included earlier, so that it's set by the time tegra.h needs to use it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | OMAP3: igep00x0: Enable required clocks for GPIO that are used.Enric Balletbo i Serra2014-03-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable required clocks for GPIO to fix a boot issue introduced by commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d (arm: omap3: Enable clocks for peripherals only if they are used). Without this patch the u-boot freezes after the following messages OMAP36XX/37XX-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 Ghz IGEPv2 + LPDDR/NAND I2C: ready DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 Diving into the issue, the sequence that produces the u-boot freezes is setup_net_chip |--> gpio_direction_out |--> _set_gpio_dataout |--> __raw_writel To avoid this we just need enable the clocks for GPIOs that are used, but it would be interesting implement a mechanism to protect these situations and make sure that the clock is enabled when we request a GPIO. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| * | | board/BuR/common: fix phy addressesHannes Petermaier2014-03-06-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | B&R boards are using Phy Addresses 'one' and 'two', prior this was defined through #define PHYADDR 1 within a header file. Now this is addresses are given with device-driver structure. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| * | arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootupStefan Roese2014-03-04-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the switch may be re-configured for VLAN usage in Linux (or any other OS), lets reset the switch to its default register values upon power-up. Otherwise network might not be available in U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com>
| * | ARM: AM43xx: Change DDR3 Reset ValueDave Gerlach2014-03-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | ARM: AM43xx: Write sdram_config to secure_emif_sdram_configDave Gerlach2014-03-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The register secure_emif_sdram_config in control module is copied to the EMIF sdram_config register when it is coming out of DeepSleep0 in order to ensure that the EMIF comes up for the correct type of DDR. Without this, resume can hang from within the kernel. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | ARM: AM43xx: EMIF: configure self-refresh entry delayDave Gerlach2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the desired delay in cycles that the EMIF waits without an access to enter self-refresh, in this case 8192 cycles. With this, code desiring to enter self refresh only has to toggle one bit to enable it. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | ARM: AM43xx: Add Ethernet boot support to SPLMugunthan V N2014-03-04-4/+8
| | | | | | | | | | | | | | | | | | | | | Add Ethernet Boot support to SPL Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: AM4372: Update EMIF registers for DDR3Lokesh Vutla2014-03-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: DRA7xx: add support for reading cpsw 2nd mac from efuseMugunthan V N2014-03-04-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also correct the bit masking of mac id read from the efuse. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: AM335x: add support for reading cpsw 2nd mac address from efuseMugunthan V N2014-03-04-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also adding mii command support to am335x common config. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVMMugunthan V N2014-03-04-2/+162
| | | | | | | | | | | | | | | | | | | | | | | | Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected to RMII and RGMII phy respectively and enable cpsw in config. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: AM43xx: clocks: Enable CPGMAC clock controlMugunthan V N2014-03-04-0/+1
| | | | | | | | | | | | | | | | | | Enable CPGMAC clock control for AM43xx to use ethernet in U-Boot Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | drivers: net: cpsw: add support to have phy address from cpsw platform dataMugunthan V N2014-03-04-33/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-03-10-997/+149
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| * | | usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-995/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | | usb: ehci: fully align interrupt QHs/QTDsStephen Warren2014-03-10-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These data structures are passed to cache-flushing routines, and hence must be conform to both the USB the cache-flusing alignment requirements. That means aligning to USB_DMA_MINALIGN. This is important on systems where cache lines are >32 bytes. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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