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* arm: rmobile: Add support R8A7793Nobuhiro Iwamatsu2014-11-10-1/+2431
| | | | | | | | Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Merge branch 'rmobile' of git://www.denx.de/git/u-boot-shTom Rini2014-11-05-21/+78
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| * arm: rmobile: alt: Add VFAT filesystem supportNobuhiro Iwamatsu2014-11-04-0/+6
| | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: alt: Add support USB and USB commandsNobuhiro Iwamatsu2014-11-04-0/+7
| | | | | | | | | | | | | | | | This adds support for USB commands and USB storage device. Signed-off-by: Yoshiyuki Ito <yoshiyuki.ito.ub@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: alt: Fix typo of SCIF idNobuhiro Iwamatsu2014-11-04-3/+3
| | | | | | | | | | | | | | Alt board use SCIF2, not SCIF0. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: alt: Remove RAM address initializationNobuhiro Iwamatsu2014-11-04-1/+0
| | | | | | | | | | | | | | | | | | | | Since board info structure is not still set up, the setting of RAM address causes illegal access. Therefore the setting of RAM address is removed. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: koelsch: Remove RAM address initializationNobuhiro Iwamatsu2014-11-04-1/+0
| | | | | | | | | | | | | | | | | | | | Since board info structure is not still set up, the setting of RAM address causes illegal access. Therefore the setting of RAM address is removed. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: lager: Remove RAM address initializationNobuhiro Iwamatsu2014-11-04-1/+0
| | | | | | | | | | | | | | | | | | | | Since board info structure is not still set up, the setting of RAM address causes illegal access. Therefore the setting of RAM address is removed. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: alt: Add external RAM bootNobuhiro Iwamatsu2014-11-04-1/+15
| | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0x70000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: koelsch: Add external RAM bootNobuhiro Iwamatsu2014-11-04-4/+19
| | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0x70000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: lager: Add external RAM bootNobuhiro Iwamatsu2014-11-04-3/+21
| | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0xB0000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: lager: Fix change of the CPU frequencyNobuhiro Iwamatsu2014-11-04-0/+7
| | | | | | | | | | | | | | | | | | The change of the CPU frequency is waited for until PLL0ST of the PLLECR is set to 1. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: r8a7790: Update initialize L2 cacheNobuhiro Iwamatsu2014-11-04-9/+2
| | | | | | | | | | | | | | | | | | | | | | Initialization of L2CTLR[5] was set only as R8A7790 by commit 237faf095fb43abbed6e40266ef7efccc8b9308b. However, initialization of cash needs to be performed continuously. This changes into the processing which continues initialization of L2CTLR[5] into L2CTLR cash and performs it. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-05-40/+1823
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| * | arm: mx6: cm_fx6: detect 1GB DRAM correctly on soloNikita Kiryanov2014-11-05-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 1GB DRAM configuration on mx6 solo uses 2 chip selects, but the code tests 1GB DRAM configuration as if it is all present on one chip select, and thus cannot see the full range of available memory. Refactor the check to detect 1GB DRAM correctly. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | arm: mx6: cm_fx6: change issd gpio orderNikita Kiryanov2014-11-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the order in which GPIOs are toggled in SATA init sequence to accomodate both SanDisk and Phison SSDs. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | novena: Add MAINTAINERS fileFabio Estevam2014-11-03-0/+6
| | | | | | | | | | | | | | | | | | | | | Commit f91c09acf5c58c ("ARM: mx6: Add support for Kosagi Novena") missed to add a MAINTAINERS file, so add Marek as the maintainer. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm, imx, spi: detect spi flash again on aristainetos boardHeiko Schocher2014-11-03-1/+7
| | | | | | | | | | | | | | | | | | | | | 155fa9af95a "spi: mxc: fix sf probe when using mxc_spi" break spi flash detection on the aristainetos board. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | imx: mx6 sabreauto: Add board support for USB EHCIYe.Li2014-11-03-0/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6slevk: Add support for USDHC1 and USDHC3 slotsYe.Li2014-11-03-7/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are three SD/MMC sockets on mx6slevk boards. Implements the full support for them. The default boot socket is USDHC2, so the MMC environment is set to that device. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sl: Add IOMUX setting for USDHC1-3Ye.Li2014-11-03-0/+19
| | | | | | | | | | | | | | | | | | Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6: Enable high frequency clock source for GPTYe.Li2014-11-03-0/+1
| | | | | | | | | | | | | | | | | | | | | Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that 24Mhz OSC clock source will be selected for GPT on all MX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-11-03-0/+17
| | | | | | | | | | | | | | | | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz sourceYe.Li2014-11-03-0/+4
| | | | | | | | | | | | | | | | | | | | | For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-11-03-0/+2
| | | | | | | | | | | | | | | | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: gpt: Add High frequency clock source support for GPTYe.Li2014-11-03-9/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will select a high frequency clock as clock source. Otherwise, the GPT will stay to use 32Khz OSC as clock source. In the implementation, since only the GPT on i.MX6 series provide the clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6 compile the driver), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they don't have the 24Mhz OSC clock source option, so also select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imximage: Fix the bootdata.size calculationYe.Li2014-11-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In system boot chapter of i.MX6 reference manual, the "Image Vector Table" figure shows the bootdata.start points to the beginning of the destination memory. It means the bootdata.size should contain the IVT offset part, but the calculation in imximage tool does not have. We found this issue when booting from QuadSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. After checked the destination memory where the image is loaded to, there are hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, for the booting devices using smaller IVT offset, such as SD and SPI booting, they are not easy to reproduce. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | arm: mxs: Define bootscript env variable on m28evkMarek Vasut2014-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch below failed to define the variable, so define it to make it consistent with M53EVK. commit a428ac914b2b6db851c1feac98622f2d9844db45 Author: Lothar Rubusch <lothar@denx.de> Date: Thu Jun 26 11:01:29 2014 +0200 ARM: m28evk: Update default environment Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: arch-mx6: typo fixes in crm_regs.hSoeren Moch2014-10-30-4/+4
| | | | | | | | | | | | | | | | | | fix typos in video pll related register names and bit defines Signed-off-by: Soeren Moch <smoch@web.de>
| * | mtd: nand: mxs: Add ECC geometry for 2048b/112b NANDMarek Vasut2014-10-30-2/+7
| | | | | | | | | | | | | | | | | | | | | Add ECC geometry for NAND which has 2048b pagesize and 112b OOB size. This is for example Macronix MX30LF2G28AB chip. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: imx6: fix typos in CCM_ANALOG_PLL_VIDEO_DENOM register nameAnatolij Gustschin2014-10-30-1/+1
| | | | | | | | | | | | | | | | | | Fix name for Video PLL denominator register. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | novena: Fix ethernet PHY reset sequenceNikolay Dimitrov2014-10-30-21/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes conflict between PHY pins becoming outputs after reset and imx6 still driving the pins. It also fixes the reset timing as recommended by the PHY datasheet. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | ot1200: rework card detect for eMMCChristian Gmeiner2014-10-30-3/+4
| | | | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | ot1200: add support for usdhc4Christian Gmeiner2014-10-30-5/+49
| | | | | | | | | | | | | | | | | | | | | On the 'mr' variant switching to 'mmc dev 1' will result in "MMC: no card present". Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | ot1200: add feature padsChristian Gmeiner2014-10-30-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The older 'mr' variant and the generic variant of the OT1200 differ in some places. As the name suggests the generic variant supports more boot devices. In order to be compatible with the 'mr' variant we define some 'feature' GPIOs. On the 'mr' variant this pads are not connected so we define their state with the help of the internal pullups. On the generic variant this GPIOs are connected and represent the state of the hardware. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | tqma6: fix typo in header guard defineMarkus Niebel2014-10-30-1/+1
| | | | | | | | | | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | tqma6: fix sf detectionMarkus Niebel2014-10-30-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way to define a GPIO line, which can be used to force CS high across multiple transactions. In order to fix sf detection change board code to make use of board_spi_cs_gpio(..). Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | mx6sabresd: Add Seiko WVGA panel supportFabio Estevam2014-10-30-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the 4.3'' Seiko WVGA parallel display. In order to direct the splash screen to the Seiko display: => setenv panel SEIKO-WVGA => save => reset Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | ARM: mx6: Add support for Kosagi NovenaMarek Vasut2014-10-30-1/+1282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Kosagi Novena board. Currently supported are: - I2C busses - FEC Ethernet - MMC0, MMC1, Booting from MMC - SATA - USB ports - USB Ethernet Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Nikolay Dimitrov <picmaster@mail.bg> Reviewed-by: Nikolay Dimitrov <picmaster@mail.bg>
| * | board: wandboard: add usb storageJeroen Hofstee2014-10-30-0/+9
| | | | | | | | | | | | | | | | | | Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge git://www.denx.de/git/u-boot-sunxiTom Rini2014-11-05-199/+2403
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| * | | dm: sunxi: Request USB vbus gpioHans de Goede2014-11-05-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary for the device-model enabled builds to work properly. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | dm: sunxi: Request card detect gpioHans de Goede2014-11-05-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary for the device-model enabled builds to work properly. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | dm: sunxi: Add support for serial using driver modelSimon Glass2014-11-05-6/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the designware serial UART used on sunxi. This just redirects to the normal ns16550 driver. Add a stdout-path to the device tree so that the correct UART is chosen. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | dm: sunxi: Modify the GPIO driver to support driver modelSimon Glass2014-11-05-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds driver model support to the sunxi GPIO driver, using the device tree to trigger binding of the driver. The driver will still operate without driver model too. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | dm: sunxi: Make sure that GPIOs are requestedSimon Glass2014-11-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The scsi_init() function uses a GPIO so should request it. There is no way to return an error here, and the request may be made multiple times, so just ignore errors for now. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | dm: sunxi: Add pinmux functions which take a bank parameterSimon Glass2014-11-05-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With driver model we will have access to a bank pointer, so we want to use it rather than converting back to a number, and then back to a bank pointer. Add functions to provide this feature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | dm: sunxi: Add a new config for an FDT-based pcDuino3Simon Glass2014-11-05-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now we won't want to mess with the existing configurations. Create a new one which will enable device tree and driver model. Note that this brings the device tree binary into u-boot-sunxi-with-spl.bin. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | dm: sunxi: dts: Add sun7i device tree filesSimon Glass2014-11-05-0/+1775
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small portion of these, but we may as well have something to look forward to. The total compiled size is about 25KB. Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: kconfig: Add %_felconfig rule to enable FEL build of sunxi platforms.Ian Campbell2014-11-05-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | $ make BOARD_felconfig is more convenient than $ make BOARD_defconfig $ echo CONFIG_SPL_FEL=y >> .config $ echo CONFIG_SPL_FEL=y >> spl/.config Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-11-06 11:15:07 +0000