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* MLK-11825 imx: mx6dqp: update ddr script to 1.13rel_imx_3.14.52_1.1.1_garel_imx_3.14.52_1.1.0_gal5.1.1_2.1.0-gaimx_v2015.04_3.14.52_1.1.0_gaPeng Fan2015-11-09-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd 1.13<-1.12: Change log: 1. Remove 20c4080 1.12<-1.10 Change log: 1. NoC register DDRCONF change to 0 which is compatible for only CS0 is used on board 2. Change 2 values to compatible with our DDR aid script, these two registers doesn’t have any effect on current system tRPA = 0; //this bit only used in DDR2 mode tAOFPD/tAONPD=0x4; //These register only works when MDPDC. SLOW_PD = 1 which is 0 in script Test results: One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed 60 hours memtester stress teset. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7)
* Revert "MLK-11408-2 imx: mx7d: Isolate 26 IP resources to domain 0 for A core"Ye.Li2015-11-09-55/+0
| | | | This reverts commit e7d4767331f1a2cbef61b4e89beb73731f267499.
* Revert "MLK-11408-1 imx: mx7d: Add mx7d RDC driver support"Ye.Li2015-11-09-190/+0
| | | | This reverts commit 3b548a3ddf03dcbb646912ef7bbdd3cdb2daf81a.
* MA-7157 Check the error log in fastboot flashzhang sanshan2015-11-05-0/+2
| | | | | | | | The fastboot.exe will get var partition-type:* firstly when "fastboot flash * *". The uboot did not support get var partition-type: default. This patch mask info the error when gat cat partition-type. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MLK-11823 USB:gadget Fix USB port interface issue in ci_udc driverYe.Li2015-11-04-1/+1
| | | | | | | | | | | | | | The ci_udc driver tries to use the ULPI interface for the USB OTG controller, but this type is not supported by all i.MX6 and i.MX7 platforms. When setting to ULPI, other platforms except the 6UL refuse the settings and keep default value. But on 6UL, the PTW bit of PORTSC1 register which is documented as RO can change. This cause the interface setting problem with USB PHY. Fix the issue by removing the ULPI setting for i.MX6 and i.MX7. All will use default UTMI setting. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f78cbee0375dcb81b10bac2e0dcd254d0551baa9)
* MLK-11784 imx: mx7: uboot plugin change for mfgtoolYe.Li2015-11-02-0/+19
| | | | | | | | | | | Fixed the issue that mfgtool failed to download u-boot with plugin enabled. The u-boot plugin common codes should not call rom___pu_irom_hwcnfg_setup when using serial download mode. rom___pu_irom_hwcnfg_setup will load the IVT2 image from boot media, but this is invalid for USB serial download mode. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit b16ae36d2ae3fa9f536fec691a3e1bfa6f26a8d0)
* MLK-11795-02 imx: upate the pmic standby voltage for imx6qpBai Ping2015-10-30-28/+47
| | | | | | | | | | | According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC 'APS' mode in standby. we add a 25mV margin to cover the IR drop and board tolerance, so the standby voltage of VDD_SOC_IN should be setting to 1.075V. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 3c38fae6dafd3b90fae2598dcbedf6cb7aa6f6af)
* MLK-11795-01 imx: correct the vdd_arm regulator setting on imx6qpBai Ping2015-10-30-45/+101
| | | | | | | | | | on i.MX6QP SDB board, the SW1A/B/C regulator is used by VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage setting for VDD_ARM_IN should be corresponding to SW2. So fix the regulator mismatch issue on i.MX6QP SDB board. Signed-off-by: Bai Ping <b51503@freescale.com> (cherry picked from commit 55a80625e81ea9ff5a5286f1d2183a2f0900f5c3)
* MLK-11799 imx: mx6qpsdb: update ddr script to 1.10Peng Fan2015-10-30-4/+4
| | | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1 Main change: (SDB board ddr density is different) 1. tRFC is different with density, tXS/tXPR refers tRFC Test Results: 2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 603b89c8990868c51b1546db4877d198358485ff)
* MLK-11767:imx: Modify the u-boot ENV offset for NAND storageYe.Li2015-10-27-7/+7
| | | | | | | | The current 36M offset will conflict with NAND FCB firmware2 when the nand chip block is 1MB size. This patch change it to 36M + 1M offset, so the redundant u-boot at firmware2 will not be broken. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11753 imx: mx6dqp: update ddr script to v1.09Peng Fan2015-10-23-7/+17
| | | | | | | | | | | | | | | | | | | | | | ddr script update to 1.09: http://compass.freescale.net/livelink/livelink?func=ll&objId= 234694528&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board. arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board. Changelog: 1. Optimize DQS duty cycle setting 2. Optimize ZQ PU/PD value Test results: 2 ARD boards. 2 6QP-SDB boards. 1 6DP-SDB board. All passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
* MLK-11721 imx: mx6q/dl/solo: default support SPI-NOR for sdb boardsPeng Fan2015-10-16-5/+5
| | | | | | | | 1. Default support SPI-NOR for imx6q/dl/solo sabresd board. 2. Fix bug for mx6soloxxx_spinor_defconfig. "nosmp" should be \"nosmp\". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11706: imx6sx: SabreSD: Expand malloc pool to 32MSandor Yu2015-10-16-1/+1
| | | | | | | | | | | Same issue as ENGR00321137, commit 3695635. GIS module need total 3M+3M+1.5M+1.5M=9M video memory. and sys reserved 16M memory for malloc. When gis module enabled, malloc may failed to allocate memory for other modules, that may cause system hang. Expand malloc pool to 32M. Signed-off-by: Sandor Yu <R01008@freescale.com>
* MLK-11718-3: imx: change the NAND env setting addressHan Xu2015-10-15-8/+8
| | | | | | | | The previous 8M address for NAND env might conflict with other boot parameters as the NAND block size increasing, change it to 36M to avoid it. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11718-2: mtd: nand: change the BCH layout setting for large oob NANDHan Xu2015-10-15-23/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | The cod change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes). Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11718-1: mtd: nand: change the maximum nange page size and oob sizeHan Xu2015-10-15-2/+2
| | | | | | | enlarge the maximum nand page size and oob size to 16k byte and 1280byte. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11675 ARM: imx: change the VDD_SOC normal voltage to 0.975VBai Ping2015-10-13-0/+37
| | | | | | | | | According to the latest datasheet(Rev. C Draft 1, 10/2015) of i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and add a 25mV margin to cover the IR drop and board tolerance. So setting VDD_SOC voltage to 0.975V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11682 imx: mx6ul: Update DDR script of 14x14 EVK board to 1.2 revYe.Li2015-10-10-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc", update it to DCD and plugin for i.MX6UL 14x14 EVK board. Updated items: Removed: 0x020c4084 0x021B0858 Value changed: 0x020E027C 0x020E0280 0x021B0008 0x021B000C 0x021B0010 0x021B0018 0x021B08C0 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Two boards passed overnight memtester stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-2 imx: mx6ul: Modify the MMDC automatic Power saving timerYe.Li2015-09-30-1/+1
| | | | | | | | The PST bit can't be set too small which will cause performance drop. Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2 commit e1ca547d198dde94c4d8278c99499ec2d2008880 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-1 imx: mx6ul: Change 14x14 LPDDR2 ARM2 memory size to 256MBYe.Li2015-09-30-2/+10
| | | | | | | The actual memory size is 256MB not 512MB, otherwise it has a wrap problem in memory and will cause memtester failed. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11622 imx6dqp-sabresd: update ddr script to v1.08Robby Cai2015-09-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable bank interleave feature to improve the performance downloaded from http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1 Before: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 15566us, 64fps, 134Mpixel/s ........ g2d blending time 20672us, 48fps, 101Mpixel/s ........ g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 8433us, 118fps, 247Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 15366us, 65fps, 135Mpixel/s ........ 180 rotation time 15374us, 65fps, 135Mpixel/s ........ 270 rotation time 15373us, 65fps, 135Mpixel/s ........ g2d flip-h time 15373us, 65fps, 135Mpixel/s ........ g2d flip-v time 15372us, 65fps, 135Mpixel/s ........ ... After: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 2810us, 355fps, 743Mpixel/s ........ g2d blending time 4025us, 248fps, 518Mpixel/s ........ g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 1846us, 541fps, 1131Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 5234us, 191fps, 399Mpixel/s ........ 180 rotation time 3176us, 314fps, 657Mpixel/s ........ 270 rotation time 5248us, 190fps, 398Mpixel/s ........ g2d flip-h time 2765us, 361fps, 755Mpixel/s ........ g2d flip-v time 3179us, 314fps, 657Mpixel/s ........ ... Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11616 imx: mx6qpsabresd: Add defconfig filesPeng Fan2015-09-24-0/+14
| | | | | | Add android and sata defconfig file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11554 imx: mx6ulevk: Modify the mtest memory end to half of PHYS_SDRAM_SIZEYe.Li2015-09-16-1/+1
| | | | | | | Since the mx6ul 9x9 evk has different DDR size with 14x14 evk, change to use the half of PHYS_SDRAM_SIZE for mtest end. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11551 imx: mx6qpsabresd: Update DDR initialization in pluginYe.Li2015-09-16-0/+180
| | | | | | The DDR initialization in plugin needs to update conformably with DCD. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11553 imx: mx7 fix typo for showclocksPeng Fan2015-09-15-2/+2
| | | | | | | This piece of code is for mx7, we should not use do_mx6_showclocks. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11549 imx: imx6ul: enlarge MMDC_MAPSR.PST to 16Anson Huang2015-09-15-1/+1
| | | | | | | | | MMDC auto power saving timer can NOT be too small, as enter/exit auto self-refresh mode too frequently may introduce too many latency for MMDC access, set it to 0x10, same as previous value on i.MX6. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11548 imx: imx6qp: add SabreSD board supportAnson Huang2015-09-15-1/+174
| | | | | | Add i.MX6QP SabreSD board support. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2015-09-10-1/+14
| | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11505 imx: mx6ul: Disable the LCDIF before system resetYe.Li2015-09-08-0/+9
| | | | | | | | | | We meet reset failure on mx6ul 9x9 evk. The internal reset logic between MMDC and functional modules seems relate with the issue. Turn off the LCDIF to stop DDR access before reset to avoid this possible internal reset problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11486 imx: mx6ul 9x9 evk correct CS0_ENDPeng Fan2015-09-04-2/+2
| | | | | | | The lpddr2 memsize of mx6ul_9x9_evk is 256MB, not 512M, so the CS0_END should be 0x47, but not 0x4F. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11490 ARM: imx: imx6ul: disable pfuze3000 low power modeAnson Huang2015-09-02-0/+5
| | | | | | | Disable PFuze3000 low power mode during standby mode, otherwise, if the power consumption exceed the threshold, PFuze will reboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11478 imx: mx6ul: Add QSPINOR boot support on mx6ul 9x9 evk boardYe.Li2015-09-01-0/+5
| | | | | | Add new build target: mx6ul_9x9_evk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11427 imx: mx7d: Update DDR script for mx7d sabresd boardYe.Li2015-09-01-23/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated items: memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001 This is just enable when LPDDR4 is enabled . memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046 T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45) memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083 PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81 memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000 DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68 memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004 DEV_ZQINIT_X32 . Should be 16 clocks memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109 T_FAW=(40ns*528Mhz)/2)=11 memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d tXPDLL=24ns*528Mhz=13clocks File: MX7D_EVK_DDR3_1GB_32bit.ds Test result: 3 boards pass 2 days stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11461 imx: imx6ul: enable LDO bypass for 9x9 EVK boardAnson Huang2015-09-01-12/+55
| | | | | | | i.MX6UL-9x9-EVK board has PFUZE3000, so enable LDO bypass support for this board. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11433 driver: fastboot: Discard unused directoryPeng Fan2015-08-28-9/+0
| | | | | | | CONFIG_FASTBOOT is not used, since we have CONFIG_FSL_FASTBOOT and CONFIG_CMD_FASTBOOT for fastboot. "drivers/fastboot" can be discarded. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11408-2 imx: mx7d: Isolate 26 IP resources to domain 0 for A coreYe.Li2015-08-25-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. There are 26 peripherals impacted by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is set M4 to a different domain with A core. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. CM4 image will set the M4 to domain 1 only. This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11408-1 imx: mx7d: Add mx7d RDC driver supportYe.Li2015-08-25-0/+190
| | | | | | | Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC. Signed-off-by: Ye.Li <B37916@freescale.com>
* tools/imximage: set DCD pointer to NULL when its length is 0Baruch Siach2015-08-20-1/+5
| | | | | | | | | | | | | | | | | | | | | | | When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine generates is empty. This causes HAB to complain that the command is invalid. --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x0c 0x41 0x33 0x06 0xc0 0x00 0xcc 0x00 0x04 0x04 To fix this set the DCD pointer in the IVT to NULL in this case. The DCD header itself is still needed for detect_imximage_version() to determine the image version. Conflicts: tools/imximage.c cherry-picked from http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=873bf926bfbb0a667158261813115fa6819661b7 Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit 873bf926bfbb0a667158261813115fa6819661b7)
* MLK-11388 imx: mx7d: add support for mx7d 19x19 lpddr2 arm2 boardYe.Li2015-08-20-1/+285
| | | | | | | | | | This mx7d 19x19 lpddr2 arm2 board is based on 19x19 lpddr3 arm2 board with DDR changed to 512M LPDDR2. We added DDR script for LPDDR2 and a new u-boot build target: mx7d_19x19_lpddr2_arm2_config LPDDR2 script source: lpddr2_0_1.ds Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11367 imx: mx6ul: Add cma bootargs for 6ul 9x9 boardYe.Li2015-08-17-0/+6
| | | | | | | | | | | Since the i.MX6ul 9x9 evk board only has 256MB LPDDR2, while the CMA size used in kernel configuration is 320MB, so we have to set another value for the 9x9 evk board. This patch sets the cma=96M bootargs to in uboot. So the kernel will overwrite to use the new value. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11364 imx: mx6ul : Add support for i.MX6UL 9x9 EVK boardYe.Li2015-08-17-4/+306
| | | | | | | | | | | | | | The i.mx6ul 9x9 EVK shares the same base board with 6ul 14x14 EVK with two main changes on CPU board: 1. Change to use pfuze 3000. 2. Use 256MB LPDDR2 memory. This patch uses a macro CONFIG_6UL_9X9_LPDDR2 to distinguish the changes above, basing on 14x14 EVK board level codes. The new build target for the 9x9 EVK: mx6ul_9x9_evk_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MA-6987 the value of vmalloc on Kernel command line still display 400M after ↵zhang sanshan2015-08-13-1/+2
| | | | | | | | | we change it to other values(sabresd dq and auto 6qp 0812 daily build) Correct the bootargs which is printed. It should be newbootargs rather than bootimage's bootargs. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MLK-11320 ARM: imx7d: disable wdog powerdown timer for LPSRAnson Huang2015-08-05-0/+5
| | | | | | | | In LPSR mode, wdog will be reset when resume, need to disable wdog powerdown timer to avoid system reset after timeout setting of 16 seconds. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11281-2 ARM: imx7d: enable plug in mode by default for lpsr modeAnson Huang2015-08-05-0/+1
| | | | | | | | | | As we need to support LPSR mode resume and due to hardware design requirement, DCD can NOT put DRAM exit from retention mode, so only plug in mode can do that to support LPSR mode, so enabled plug in mode by default for imx7d 12x12-lpddr3-arm2 board. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11281-1 ARM: imx7d: add lpsr resume support for imx7dAnson Huang2015-08-05-0/+343
| | | | | | | | | | | | For imx7d 12x12-lpddr3-arm2 board, when system enters LPSR mode and waked up, ARM core will be reset and uboot needs to be executed first, the LPSR register contains a resume entery, if this entry is non-zero, then it means it is a resume from LPSR mode, uboot plug in code needs to make DRAM exit from retention mode then jump to the entry directly, otherwise, it is a cold boot, normal boot process will be performed. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11263-2 video: epdc: move setup_waveform_file to board commonPeng Fan2015-08-03-146/+38
| | | | | | | | | | | Since setup_waveform_file in different boards code have same implementation, move setup_waveform_file to board common code. Also rename it to board_setup_waveform_file This patch also fix a bug when using flush_cache. We should pass 'waveform_buf' to flush_cache, but not a string named 'addr'. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11263-1 video: epdc: support display logo on E-Ink screenPeng Fan2015-08-03-12/+194
| | | | | | | | | | | | | | | | | | | Support draw image on E-ink screen. 1. The image format should be PGM-P5 raw data format. 2. The image should be named epdc_logo.pgm. 3. If no epdc_logo.pgm found in the first partition(FAT), will choose to draw black border on the screen. 4. Default configuration is to draw image at pos (0,0). If 'splashpos' env is set, will choose the pos from 'splashpos'. 5. The image size should not be bigger than screen total pixel size. 6. Implement board_setup_logo_file in board/freescale/common/epdc_setup.c 7. Introudce function prototype for board_setup_logo_file. Note: i.MX7D EPDC supports advanced mode and standard mode. Since current PXP in uboot for i.MX7D not ready, only support standard mode now. advanced and standard mode needs waveform firmware's support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11299 ARM: imx7d: initialize PMIC standby mode and voltageAnson Huang2015-08-03-0/+67
| | | | | | | Datasheet Rev-B defines standby voltage as 1V for i.MX7D, we add 25mV for board level IR drop. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-10957: ARM: mx6qp: do not turn off PURobin Gong2015-07-31-1/+2
| | | | | | | | | There is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 6b0787b726e2ff32210d742d93ecd3f4bb2ae402)
* MLK-11304 MX6 SabreSD: Disable HDMI detectPeng Fan2015-07-31-1/+1
| | | | | | | | | | | | | | | As the HDMI splash screen feature is not well supported, we should not set it to be the default display. In case, users leave the 'panel' uboot environment variable empty and connect the board with a HDMI monitor, the HDMI detect funtion will work and enable the HDMI splash screen. So, this patch disables HDMI detect function so that users may only explicitly set the 'panel' variable to be 'HDMI' to use HDMI splash screen. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-11-21 12:31:51 +0000