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* powerpc: digsy_mtc: convert to generic boardAnatolij Gustschin2014-10-27-0/+2
| | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: mecp5123: convert to generic boardAnatolij Gustschin2014-10-27-0/+3
| | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* powerpc: ac14xx: convert to generic boardAnatolij Gustschin2014-10-27-0/+3
| | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: aria: convert to generic boardAnatolij Gustschin2014-10-27-0/+3
| | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: pdm360ng: convert to generic boardAnatolij Gustschin2014-10-27-0/+2
| | | | Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: mpc5121ads: convert to generic boardAnatolij Gustschin2014-10-27-0/+3
| | | | | | Also enable CONFIG_DISPLAY_BOARDINFO to get checkboard() called. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: mpc512x: fix boot breakageAnatolij Gustschin2014-10-27-0/+1
| | | | | | | | Commit d6b11fd1 (powerpc: remove MBX and MBX860T boards support) removed mbxbar field in "struct sysconf512x" by mistake and broke booting on mpc5121 boards. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Merge http://git.denx.de/u-boot-sunxiTom Rini2014-10-26-80/+1010
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| * sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig optionHans de Goede2014-10-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5 "p" value to 1 (divide by 2) as that is what those kernels are hardcoded too, in the future this may enable further workarounds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@ti.com> -- Changes in v2: -s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT. -Move the code block setting P(1) for old kernels to where P gets cleared
| * sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcodingHans de Goede2014-10-24-18/+14
| | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add clock_get_pll5p() functionHans de Goede2014-10-24-0/+15
| | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)Ian Campbell2014-10-24-2/+2
| | | | | | | | | | | | | | | | | | | | I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfigChen-Yu Tsai2014-10-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same. See: http://linux-sunxi.org/Ippo_q8h Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add support for using R_UART as consoleChen-Yu Tsai2014-10-24-0/+15
| | | | | | | | | | | | | | | | | | | | The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads. Add support for R_UART so we can have a console while using mmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Allow specifying module in prcm apb0 init functionChen-Yu Tsai2014-10-24-6/+8
| | | | | | | | | | | | | | | | | | The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add support for R_PIO gpio banksHans de Goede2014-10-24-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add basic A23 supportChen-Yu Tsai2014-10-24-3/+35
| | | | | | | | | | | | | | | | | | | | | | The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup. There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-2/+2
| | | | | | | | | | | | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add support for uart0 on port F (mmc0)Chen-Yu Tsai2014-10-24-1/+12
| | | | | | | | | | | | | | | | | | Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add sun8i (A23) UART0 pin mux supportChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | | | | UART0 pin muxes on the A23 have a different function value. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Fix reset command on sun6i/sun8iChen-Yu Tsai2014-10-24-0/+30
| | | | | | | | | | | | | | | | | | | | The watchdog on sun6i/sun8i has a different layout. Add the new layout and fix up the setup functions so that reset works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> [ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
| * ARM: sunxi: Add sun6i/sun8i timer block register definitionChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | The RTC hardware has been moved out of the timer block on sun6i/sun8i. In addition, there are more watchdogs available. Also note that the timer block definition is not completely accurate for sun5i/sun7i. Various blocks are missing or have been moved out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Move watchdog register definitions to separate fileChen-Yu Tsai2014-10-24-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | On later Allwinner SoCs, the watchdog hardware is by all means a separate hardware block, with its own address range and interrupt line. Move the register definitions to a separate file to facilitate supporting newer SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Fix build break when CONFIG_MMC is not definedChen-Yu Tsai2014-10-24-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI. This is used when we want to use uart0 from port F, which conflicts with mmc0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add CONFIG_MACH_TYPE defines to sun4i, sun5i and sun7iHans de Goede2014-10-24-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Many people are still using old linux-sunxi-3.4 kernels on sunxi devices, adding the proper MACH_TYPE defines for this allows people to switch to upstream u-boot, so that we can stop maintaining the linux-sunxi u-boot fork. These machine-ids are all properly registered at: http://www.arm.linux.org.uk/developer/machines/ Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Kconfig: Unify sunxi Kconfig codeHans de Goede2014-10-24-27/+5
| | | | | | | | | | | | | | | | Unify the sunxi Kconfig code, instead of having separate code blocks for each of sun4i - sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Enable second sdcard slot found on some boardsHans de Goede2014-10-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the second sdcard slot found on some boards. Note that we do not set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful, Except for on the Mele-M3 where the second sdcard is an eMMC, from which the device can also boot, and there we want to have both in the SPL, so that a single u-boot binary can both from both. So for the M3 we do prefix the defconfig setting with the special "+S:" syntax so that it applies to the SPL too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Use PG3 - PG8 as io-pins for mmc1Hans de Goede2014-10-24-3/+5
| | | | | | | | | | | | | | | | | | | | None of the known sunxi devices actually use mmc1 routed through PH, where as some devices do actually use mmc1 routed through PG, so change the routing of mmc1 to PG. If in the future we encounter devices with mmc1 routed through PH, we will need to change things to be a bit more flexible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: When we've both mmc0 and mmc2, detect from which one we're bootingHans de Goede2014-10-24-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're booting, and make that one "mmc dev 0" so that a single u-boot binary can be used for both the onboard eMMC and for external sdcards. When we're booting from mmc2, we make it dev 0 because that is where the SPL will load the tertiary payload (the actual u-boot binary in our case) from, see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Turn MMC_SUNXI_SLOT_EXTRA into a proper Kconfig optionHans de Goede2014-10-24-1/+9
| | | | | | | | | | | | | | | | | | Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL check is not necessary with Kconfig, because only options explicitly marked as also being for the SPL get set during SPL builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add mmc card-detect functionalityHans de Goede2014-10-24-0/+48
| | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Add Colombus board defconfigChen-Yu Tsai2014-10-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | The Colombus board is an A31 evaluation board from WITS Technology. Maxime has kindly agreed to maintain this board. [1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.html Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Add basic A31 supportMaxime Ripard2014-10-24-1/+40
| | | | | | | | | | | | | | | | | | | | | | Add a new sun6i machine that supports UART and MMC. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef around mmc and smp code, drop MACH_TYPE] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Setup the A31 UART0 muxingMaxime Ripard2014-10-24-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens@csie.org: reorder #ifs by SUN?I] [wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Define UART0 pins for A31Chen-Yu Tsai2014-10-24-0/+3
| | | | | | | | | | | | | | UART0 is the default debug/console UART on the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi-mmc: Add mmc support for sun6i / A31Hans de Goede2014-10-24-5/+11
| | | | | | | | | | | | | | | | | | | | | | The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use setbits_le32 for reset control, drop obsolete changes, rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Add clock supportChen-Yu Tsai2014-10-24-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. This includes changes from the following commits from u-boot-sunxi: a92051b ARM: sunxi: Add sun6i clock controller structure 1f72c6f ARM: sun6i: Setup the UART0 clocks 5f2e712 ARM: sunxi: Enable pll6 by default on all models 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31 12e1633 ARM: sun6i: Add initial clock setup for SPL 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup. 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6} c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: styling fixes reported by checkpatch.pl] [wens@csie.org: drop unsupported SPL code block and unused gpio.h header] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Add support for the power reset control module found on the A31Oliver Schinagl2014-10-24-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block modules, and also PLL biasing in the main clock module. This patch adds the register definitions, and also enables the clocks and resets for the RTC block PIO (pin controller) and P2WI (push-pull 2 wire interface) which is used to talk to the PMIC. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: spacing fixes reported by checkpatch.pl] [wens@csie.org: Use setbits helper in PRCM init function] [wens@csie.org: rephrase commit message to explain what the hardware supports and what we actually enable] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sun6i: Add base address for the new controllers in A31Oliver Schinagl2014-10-24-0/+9
| | | | | | | | | | | | | | | | | | A31 has several new and changed memory address. This patch adds them. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not definedChen-Yu Tsai2014-10-24-1/+7
| | | | | | | | | | | | | | | | | | BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi: Use macro values for setting UART GPIO pull-upsChen-Yu Tsai2014-10-24-3/+3
| | | | | | | | | | | | | | | | | | We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add support for the Mele M3 boardHans de Goede2014-10-24-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The Mele M3 is yet another Allwinnner based Android top set box from Mele. It uses a housing similar to the A2000, but without the USM sata storage slot at the top. It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices), 100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * mmc: sunxi: add SDHC support for sun6i/sun7i/sun8iWills Wang2014-10-24-0/+3
| | | | | | | | | | | | | | Allwinner A20/A23/A31's SD/MMC host support SDHC High Capacity feature. Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sun7i: Add support for Olimex A20-OLinuXino-LIME2Iain Paton2014-10-24-0/+43
| | | | | | | | | | | | | | | | | | | | This adds support for the Olimex A20-OLinuXino-Lime2 https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2 Differences to previous Lime boards are 1GB RAM and gigabit ethernet Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-10-26-8/+1903
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| * | musb: fix warning in include/linux/usb/musb.hIgor Grinberg2014-10-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warning by including linux/compat.h: include/linux/usb/musb.h:110: warning: 'struct device' declared inside parameter list include/linux/usb/musb.h:110: warning: its scope is only this definition or declaration, which is probably not what you want Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | ARM: rpi_b: enable USB/DHCP/PXE in bootcmdStephen Warren2014-10-22-11/+14
| | | | | | | | | | | | | | | | | | | | | USB support must be enabled before config_distro_bootcmd.h is included for bootcmd to include USB-related functionality. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | ARM: rpi_b: query internal MAC address from firmwareStephen Warren2014-10-22-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | The built-in SMSC 95xx chip doesn't know its own MAC address. Instead, we must query it from the VC firmware; it's probably encoded in fuses on the BCM2835. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | arm: rpi: Enable USB support on RPiMarek Vasut2014-10-22-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DWC2 USB, storage and ethernet support. Tested on RPi B+. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | usb: dwc2: Add driver for Synopsis DWC2 USB IP blockOleksandr Tymoshenko2014-10-22-1/+1843
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi. This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question. Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835). Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Vince Bridgers <vbridger@altera.com> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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