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* add weak entry definitionDavid Feng2014-01-09-0/+4
| | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* cmd_pxe: remove compiling warningsDavid Feng2014-01-09-2/+2
| | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* fdt_support: 64bit initrd start address supportDavid Feng2014-01-09-32/+34
| | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-08-947/+13
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| * ARM: dra7_evm: read mac address properly from e-fuseMugunthan V N2014-01-07-4/+4
| | | | | | | | | | | | | | Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * arm: omap: cm_t35: enable gpio bank 5 clocks explicitlyNikita Kiryanov2014-01-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Following commit "arm: omap3: Enable clocks for peripherals only if they are used" (f33b9bd3984fb11e1d8566a866adc5957b1e1c9d) it is now necessary to enable clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for scf0403 lcd support. Enable GPIO bank 5 clocks. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * ARM: twister: add missing gpio clock initJeroen Hofstee2014-01-07-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d breaks boards which do not explicitly enable the gpio clocks. This causes the twister spl to hang, since it uses the no longer enabled gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board. Cc: Stefano Babic <sbabic@denx.de> Cc: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Stefano Babic <sbabic@denx.de>
| * ARM: tam3517-common: fix nand spl bootJeroen Hofstee2014-01-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme" removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config, causing the spl nand boot to fail. Add it back, so derived boards boot again. Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Raphael Assenat <raph@8d.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Stefano Babic <sbabic@denx.de>
| * TI:omap3: Drop omap3_zoom2Tom Rini2014-01-07-943/+2
| | | | | | | | | | | | | | The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com>
| * cam_enc_4xx: Set CONFIG_SYS_NAND_MAX_OOBFREE / CONFIG_SYS_NAND_MAX_ECCPOSTom Rini2014-01-07-0/+2
| | | | | | | | | | | | | | | | | | | | With the changes to make OOBFREE/ECCPOS configurable but default to larger, we need to set these config options for the space savings they provide. Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* | arm/km: fix i2c mux define for km_kirkwood_128m16 targetHolger Brunck2014-01-06-1/+1
| | | | | | | | | | | | | | | | Due to the i2c mux rework in u-boot we now have only to specify the busnumber and not the whole mux configuration. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de>
* | arm/km: add support for km_kirkwood_128m16 boardKarlheinz Jerg2014-01-06-0/+11
| | | | | | | | | | | | | | | | | | | | The board is similar to the standard km_kirkwood board. From a u-boot point of view, the only difference is an increased 256 MiB DRAM (128M16). A board based on this design is for example the SUP12. Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | kirkwood: ib62x0: use device tree and update configLuka Perkov2014-01-06-15/+23
|/ | | | | | Signed-off-by: Luka Perkov <luka@openwrt.org> CC: Prafulla Wadaskar <prafulla@marvell.com> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-1319/+5196
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| * board:trats2: fix default partitions and mmc envPiotr Wilczek2013-12-31-1/+2
| | | | | | | | | | | | | | | | | | This patch add uuid disk to defualt partions necessary to restore gpt partitions and fixes mmcdev environmental variable. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * board:trats1:trats2: fix adapter numberPiotr Wilczek2013-12-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This fix is necessary after increased by one the number of adapters in s3c24x0 driver. Tested on Trats and Trats2. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SPL: EXYNOS: Prepare for variable size SPL supportRajeshwari Birje2013-12-30-44/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When variable size SPL is used, the BL1 expects the SPL to be encapsulated differently: instead of putting the checksum at a fixed offset in the SPL blob, prepend the blob with a header including the size and the checksum. The enhancements include - adding a command line option, '--vs' to indicate the need for the variable size encapsulation - padding the fixed size encapsulated blob with 0xff instead of random memory contents - do not silently truncate the input file, report error instead - no need to explicitly closing files/freeing memory, this all happens on exit; removing cleanups it makes code clearer - profuse commenting - modify Makefile to allow enabling the new feature per board Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Config: Add initial config for SMDK5420Rajeshwari Birje2013-12-30-280/+347
| | | | | | | | | | | | | | | | | | | | Adding initial config for SMDK5420 to build and boot U-Boot over Exynos based SMDK5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * DTS: Add dts support for SMDK5420Rajeshwari Birje2013-12-30-190/+441
| | | | | | | | | | | | | | | | | | | | | | This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add base patch for SMDK5420Rajeshwari Birje2013-12-30-1/+229
| | | | | | | | | | | | | | | | | | | | | | Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-16/+390
| | | | | | | | | | | | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-58/+484
| | | | | | | | | | | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1679
| | | | | | | | | | | | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-30-0/+167
| | | | | | | | | | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-30-0/+837
| | | | | | | | | | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-30-1/+48
| | | | | | | | | | | | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-527/+437
| | | | | | | | | | | | | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-3781/+3439
|\ \ | |/ |/| | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-1/+28
| | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6Otavio Salvador2014-01-03-10/+11
| | | | | | | | | | | | | | | | | | | | The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * ARM: mx6: Change the FDT loading address to avoid overlapingOtavio Salvador2014-01-03-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes allow for the DeviceTree and initrd relocation fixing the boot of FSL 3.10.9-1.0.0-alpha kernel. This changes following boards: - mx6sabreauto - mx6sabresd - wandboard - udoo - nitrogen6x - cgtqmx6eval The reasoning, as explained by Hui Liu, is: ,---- | The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel | Boot up, it will decompress the compressed kernel image and place the decompressed | kernel image at the low end of the DDR memory and start running from it. If the | decompressed kernel image is bigger for example than 16M, it may over written the | fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000 | | To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override | Since we will not likely have one kernel image larger than 128MB. `---- Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx28evk: Extend environment to easy write of NAND systemOtavio Salvador2014-01-03-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds following new targets: - update_nand_kernel - update_nand_fdt - update_nand_filesystem and to avoid confusion, the 'update_nand_full' has been renamed to 'update_nand_firmware_full'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx28evk: Add 'nandboot' environment commandOtavio Salvador2014-01-03-1/+17
| | | | | | | | | | | | | | | | | | This reads the kernel, ftd and boot into ubifs filesystem. While on that, the SD firmware filename definition has been moved next to the other SD related commands. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx28evk: Use 512k for fdt partition to align itOtavio Salvador2014-01-03-1/+1
| | | | | | | | | | | | | | | | Using 512k for fdt partition allow it to be aligned with the other small partitions and 512k erase block size. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macroOtavio Salvador2014-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio Estevam <fabio.estevam@freescale.com> and Eric Bénard <eric@eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+65
| | | | | | | | | | | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Add the required LDO ramp up delayFabio Estevam2014-01-02-3/+20
| | | | | | | | | | | | | | | | | | | | When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Introduce set_ldo_voltage()Fabio Estevam2014-01-02-7/+26
| | | | | | | | | | | | Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam2014-01-02-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-3/+1
| | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabre_common.h: Add CONFIG_CMD_FUSE supportFabio Estevam2014-01-02-0/+5
| | | | | | | | | | | | | | Add CONFIG_CMD_FUSE option, so that the fuse API can be used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * doc: README.fuse: Add an example on how to use the fuse API on mx6qFabio Estevam2014-01-02-0/+76
| | | | | | | | | | | | | | | | | | | | When using the fuse API in U-boot user must calculate the 'bank' and 'word' values. Provide a real example on how to calculate such values for the mx6q. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * MX6: fix sata compilation for i.MX6Stefano Babic2013-12-19-1/+2
| | | | | | | | | | | | | | Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks board with SATA support, because sata is not compiled. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | | | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
| * ARM: mxs: tools: Fix errno handling in strtoul() invocationMarek Vasut2013-12-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to NOTE in strtoul(3), the errno must be zeroed before strtoul() is called. Zero the errno. The NOTE reads as such: Since strtoul() can legitimately return 0 or ULONG_MAX (ULLONG_MAX for strtoull()) on both success and failure, the calling program should set errno to 0 before the call, and then determine if an error occurred by checking whether errno has a nonzero value after the call. This issue was detected on Fedora 19 with glibc 2.17 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * mx6sabresd: Fix LVDS width and color formatFabio Estevam2013-12-17-3/+3
| | | | | | | | | | | | | | | | mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signalsFabio Estevam2013-12-17-0/+9
| | | | | | | | | | | | | | | | HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mx53: video: Add IPUv3 LCD support for M53EVKMarek Vasut2013-12-17-0/+89
| | | | | | | | | | | | | | | | This patch adds support for the AMPIRE 800x480 LCD panel that is available for M53EVK. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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