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* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-29-0/+38
| | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
* MLK-10674-1 imx: mx6qpsabreauto Update to 1.05 DDR ScriptPeng Fan2015-04-29-1/+9
| | | | | | | | | | | | | | | | | | | | Update to 1.05 ddr script, url: http://compass.freescale.net/livelink/livelink?func=ll& objId=233944823&objAction=browse&viewType=1 File name: arik_r2_sabre_ddr3_528_1.05c.inc Update: Read latency Aging control for IPU1/PRE0/PRE3 Aging control for IPU2/PRE1/PRE2 Test results: 3 boards passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
* MLK-10504 imx: mx6dqarm2: Fix CCM setting for lpddr2 400Mhz supportYe.Li2015-04-29-0/+6
| | | | | | | | | | | | | | | | | | Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 7490062ff86e1132b95bf153091f28f7940c0cf9)
* MLK-10658 imx: mx7d 12x12 arm2: Update plugin codes to use latest DDR scriptYe.Li2015-04-29-23/+27
| | | | | | | | | | The LPDDR3 intialization in plugin codes were missed to update in previous DDR script upgrading. So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 1874cec3a70adde2ea911a9c155fb41c43ccab61)
* MLK-10655 Video: Fix second line string display issueYe.Li2015-04-29-4/+5
| | | | | | | | | | The string display on second line repeats the last word of first line and does not show full. This is the bug introduced by the fixing to MLK-10542. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ac430cee8c42f0acad9e126631d772b99f1166ea) (cherry picked from commit ff62c5b275a9b5e47d570d3eb10622799bf12070)
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
* MLK-10774-46 imx:mx6sx use correct GPR addressPeng Fan2015-04-29-1/+1
| | | | | | Use correct GPR address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-45 imx:mx6sx add SION for i2c pin muxPeng Fan2015-04-29-20/+20
| | | | | | | | Add SION for i2c pin mux, otherwise will cause error. Found this problem on mx6sxsabreauto board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-44 imx:mx6 fix is_soc_revPeng Fan2015-04-29-1/+1
| | | | | | | is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-43 imx:mx7d fix DEFAULT_FDT_FILEPeng Fan2015-04-29-5/+5
| | | | | | should add '\' to string, otherwise this macro will be ignored. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10542 video: Support multiple lines version string displayYe.Li2015-04-29-7/+23
| | | | | | | | | | | | The caculation of left space for version string is not correct, should use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space than actual have and cause string to overlay logo picture. Also current version string display only supports two lines words at max. This also causes overlay when the LCD pixel colume size is not enough. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ed53487d36a886fb4557088804a4b5232b168889)
* MLK-10617 imx: mx7d 12x12 arm2: Update LPDDR3 script to 7D_lpddr3_0_2.ds5Ye.Li2015-04-29-1/+1
| | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] This script enable MDLL, but make it much more margin for the unlock state . [DDR stress test result] 2 boards run the memtester for 3 days, and passed. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6fa6765b0dcdad8d414931e49edf6ba65a73d23a)
* MLK-10597: arm: imx7d: extend iomuxc-lpsr IO pads config optionsAdrian Alonso2015-04-29-4/+39
| | | | | | | | | * Extend IOMUXC-LPSR IO pads configuration options * Add alternative configuration modes for IO pads from IOMUXC-LPSR Signed-off-by: Adrian Alonso <aalonso@freescale.com> (cherry picked from commit ca20aa7ca0c21b9766e0c34cfec275aaab0f11e7)
* MLK-10569 imx7d: call set_epdc_qos unconditionallyRobby Cai2015-04-29-4/+1
| | | | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. This patch remove the #ifdef to make sure set_epdc_qos be called always. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899) (cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
* MLK-10590: arm :imx7d: correct iomuxc-lpsr daisy chainAdrian Alonso2015-04-29-3/+3
| | | | | | | | | | * Correct daisy chain settings for LPSR iomux controller * Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified to be part of lpsr-iomuxc domain Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit e4fd6550b3e5458aaf5049a7e6a12d6e4443c53a)
* MLK-10522-3: imx: mx7d_12x12_ddr3_arm2: add target board supportAdrian Alonso2015-04-29-0/+750
| | | | | | | | | | | | | | * Add mx7d_12x12_ddr3_arm2 target board support * Initial support for mx7d_12x12_ddr3_arm2 target board add support for base hardware eMMC, SD and ECSPI boot. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44) Conflicts: boards.cfg
* MLK-10522-2: arm: imx7d: add iomuxc-lpsr i2c pad settingsAdrian Alonso2015-04-29-1/+4
| | | | | | | | | | | * Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings * Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS allows to access register in iomuxc controller for imx_iomux_v3_setup_pad I2C daisy chaing configuration. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit bca65c5ee1099f99b880be325c9fa0a568ab88de)
* MLK-10522-1: mx7d_arm: allow override mtest settingsAdrian Alonso2015-04-29-0/+2
| | | | | | | | | * Allow to override mtest settings for target board variants that differs on physical sdram memory size Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6173a3954b83ce22e24c62bc8ee922007b0929a6)
* MLK-10566: arm :imx7d: fix iomuxc-lpsr daisy chain settingsAdrian Alonso2015-04-29-0/+4
| | | | | | | | | | | | | | | * For IOMUXC LPSR pads when daisy chain register needs to be set the result offsets for sel_input register is incorrect as base address is 0x302C0000 and the passed offset does not resolve to the intended input sel pad register; input sel base offset should start in 0x30330000. * Add an addiotional fixed offset of 0x70000 to address the input sel offset: INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5d4612613eb2e85f1929d8cf5cb6aac6ba9e5fd7)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2015-04-29-0/+3
| | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640)
* MLK-10568 imx: mx7d arm2: Update LPDDR3 script to 7D_lpddr3_0_1.ds5Ye.Li2015-04-29-19/+16
| | | | | | | | | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelinkfunc=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] 1. Change the DDR freq to 528Mhz. 2. Disable ddr phy dll, just force a dll output. IC suspects the dll in ddr phy may unlock sometimes. The side-effect is we will lost the ability to compensate the voltage/temperature change, so it may easy to fail at H/L temperature. [DDR stress test result] 3 boards involved the two days stress test by using memtester tool. One board met a kernel oops after one day test. Other two pass the two days test. Compared to previous DDR script, the result is much positive. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 843c3c54af12cbf20e7bc912178e5a3628b78198)
* MLK-10567: Extend u-boot imximage to support check bits set/clrNitin Garg2015-04-29-15/+29
| | | | | | | | | | | Add support for HAB "Check data" all bits set and clear check functionality. Rename CHECK_DATA to CHECK_BITS_SET. Flag=0 -> (*address & mask) == 0 | All bits clear Flag=2 -> (*address & mask) == mask | All bits set Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 0836912ef7a53d1f3d65f95556a34d03b8d65399)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-04-29-0/+7
| | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
* MLK-10520 add clk_ignore_unused in i.MX7d u-boot parameterHan Xu2015-04-29-0/+2
| | | | | | | add this parameter in u-boot as a temporary workaround. Signed-off-by: Han Xu <b45815@freescale.com> (cherry picked from commit f0beee980914360c8783406ef8694974467eb07b)
* MLK-10513 mx7: HAB: Fix HAB RVT addresses to unified sectionYe.Li2015-04-29-11/+5
| | | | | | | | Incorrect hab_rvt addresses were used for getting HAB functions. Need to change to addresses in unified section. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
* MLK-10774-42 imx:mx7:thermal fix reading temperaturePeng Fan2015-04-29-10/+10
| | | | | | Fix reading temperature. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-41 imx: mx6sx: update VDDSOC standby voltagePeng Fan2015-04-29-0/+18
| | | | | | | | | | | | | This patch is from commit "f2c5102bf3763d77a227c1cba7fcd49e3db53a1d". " According the latest datasheet Rev.0,2/2015, the VDDSOC_IN voltage in standby/DSM mode is 1.05V. As we use PFM mode of pFuse and this mode has 3% tolerance issue, so the standby mode voltage should be (1.05 * 1.03) = 1.0815, we use 1.10V as the minimal step is 25mV. For i.MX6sx SDB RevB boards, the VDDARM and VDDSOC use the same supply, so the DSM voltage for VDDARM also need to be updated. " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10503 imx:mx6qp add missed macroPeng Fan2015-04-29-1/+4
| | | | | | | is_mx6dqp should be only applied for MX6 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit d860559f7913f16f7cb248f7b44140e8c1aa3ee9)
* MLK-10499 imx:mx6qp update printed cpu infoPeng Fan2015-04-29-5/+14
| | | | | | | We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 64b2be69835af80e0dbc151175617942683a3167)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2015-04-29-11/+15
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* MLK-10492-2 imx: mx7dsabresd: Add TFT43AB LCD supportYe.Li2015-04-29-10/+10
| | | | | | | | The mx7dsabresd uses new LCD TFT43AB which has 480 x 272 pixels. Update panel info for this LCD. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit e77d667b20956a37de9d367a8914ef2fe79258df)
* MLK-10492-1 imx: mx7d: Update LCDIF clock settingsYe.Li2015-04-29-7/+54
| | | | | | | | | To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
* MLK-10477-5 imx: mx7dsabresd: Add EPDC supportYe.Li2015-04-29-103/+267
| | | | | | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7dsabresd.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Since the EPDC has pinmux conflicts with ENET and QSPI. These two modules can't work at same time. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 8ba7f88f9efac9f90319b71644d3d1191f535d03)
* MLK-10477-4 imx: mx7d 12x12 lpddr3 ARM2: Add EPDC supportYe.Li2015-04-29-2/+286
| | | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7d_12x12_lpddr3_arm2.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 414824dcb77a067213849d340cf92777e6546810)
* MLK-10477-3 EPDC: Update EPDC driver head file for v2Ye.Li2015-04-29-207/+324
| | | | | | | | To support EPDC V2 on mx7d, update the mxc_epdc_fb.h for new registers layout. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 04588deb8ad368e77ec3563aa012a520faa6cade)
* MLK-10477-2 imx: mx7d: Add EPDC clock init and base addressYe.Li2015-04-29-0/+34
| | | | | | | Ungate the EPDC clock at system up if the EPDC is enabled Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f215632cb25d1076ab5c5465efdfad2212010d8d)
* MLK-10477-1 imx: mx7d: Add QoS settings for EPDCYe.Li2015-04-29-0/+34
| | | | | | | Add the QoS settings function which is used for EPDC Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
* MLK-10478 mx6: EPDC: Improve EPDC usage and configurationYe.Li2015-04-29-175/+81
| | | | | | | | | | | | | | Change to load EPDC waveform from FAT partition and allocate waveform buffer, framebuffer and working buffer in dynamic manner not static. So many EPDC configurations are removed. To enable the EPDC feature, must define CONFIG_MXC_EPDC and CONFIG_SPLASH_SCREEN. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 4d55a4124be3a3a6288c3c845d17fd9d4f2b8b43) Conflicts: include/configs/mx6slevk.h
* MLK-10774-40 imx: mx7dsabresd: Add build target for QPSI and NANDPeng Fan2015-04-29-0/+14
| | | | | | | Add targets for building u-boot to support QSPI booting and NAND booting. NAND booting can't work on mx7d TO1.0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10476 imx: mx7dsabresd: Fix 74LV driver issueYe.Li2015-04-29-8/+9
| | | | | | | | | Should write the bits to SDI in reverse order because of the bits will be shifted. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 83389e054d3cb7a905a3f81c20f395e784beb258) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-39 imx:mx6qsabreauto update video settingsPeng Fan2015-04-29-7/+91
| | | | | | Update video settings Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-38 imx: fix ecspi codePeng Fan2015-04-29-5/+25
| | | | | | | | | | | This commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 "spi: mxc: fix sf probe when using mxc_spi" introduces "board_spi_cs_gpio" function to discard gpio in CONFIG_SF_DEFAULT_CS for spi flash. Follow this rule to make imx boards work fine. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10467 mtd:spi Add ATMEL AT45DB021E supportPeng Fan2015-04-29-2/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add atmel AT45DB021E spi flash support. Since this flash is different from the spi flash that we previous use such as m25p32 and spanion spi nor flashes, pieces of code are added. 1. The default page size is 264 bytes, but the mtd/spi framework can not handle such page. So we need to configure the page size from 264 to 256 bytes. Page Size command seq “Power of 2” binary page size (256 bytes)| 3Dh 2Ah 80h A6h DataFlash page size (264 bytes) | 3Dh 2Ah 80h A7h And when probe the flash, configure the flash to 256 bytes page size, if the page size is already 256bytes, just return and do not configure it again. The page size configuration times is only about 10000, so to avoid configuring it each time. 2. Add the flash params in sf_params.c. 3. This flash support 2K block erase, add this flag. 4. The status command is 0xD7, different from others. It's polling status bit is Bit 7 -> 0 Device is busy with an internal operation. -> 1 Device is ready. This patch has been tested on mx7d 19x19 ddr3 arm2 board. And tested on mx7d 12x12 lpddr3 board. All works fine. Note: Since this flash is only 256KB, we can not test spi boot on mx7d 19x19 arm2 board. If want to test this flash, open CONFIG_SYS_USE_SPINOR. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 9b6ac1f82b09d243dc674c780abcacf0e12262c2) Conflicts: drivers/mtd/spi/sf_internal.h drivers/mtd/spi/sf_params.c drivers/mtd/spi/sf_probe.c include/spi_flash.h Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MA-6381 Add HAB support for the whole boot.imgguoyin.chen2015-04-29-25/+73
| | | | | | | | | boot.img includes kernel image, ramdisk img, dtb, and bootargs. All are critical for android security. Protect the whole boot.img with HAB. Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit 8a49e53c5b518677b46cada5df153306161f29ac)
* MLK-10453 mmc: fix possible unintialized ocrPeng Fan2015-04-29-1/+4
| | | | | | | | | | | | This commit ca4113da25b42bce44a2e7998966a47352f11613 "mmc: fix OCR Polling" does not consider cmd structure, and may leave it in uninitialized state. We can directly use op_cond_response here, since until here, op_cond_response already get the OCR value from chip. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Suggested-by: Ye.Li <B37916@freescale.com> (cherry picked from commit a033d2d43904f27778ee6a44f3e35494f9f72152)
* MLK-10448-7 imx:mx6qpsabreauto add missed macroPeng Fan2015-04-29-1/+4
| | | | | | Add CONFIG_DEFAULT_FDT_FILE macro and PHYS_SDRAM_SIZE. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10448-6 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportYe.Li2015-04-29-1/+388
| | | | | | | | | | | | | | | | | | 1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665) Conflicts: board/freescale/mx6qsabreauto/mx6qsabreauto.c boards.cfg
* MLK-10448-5 imx: mx6qp: Enable PRG clock for IPUYe.Li2015-04-29-0/+6
| | | | | | | | | | The i.MX6QP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 089f399ea07db79d6bca8fdc08b442b59eb55feb)
* MLK-10448-4 mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-04-29-1/+2
| | | | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 96e13b57ead3ed00c3a32c5373c7a2a876947f99) Conflicts: arch/arm/cpu/armv7/mx6/hab.c
* MLK-10448-3 mx6: ccm: Change the clock settings for i.MX6QPYe.Li2015-04-29-20/+57
| | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35) Conflicts: arch/arm/cpu/armv7/mx6/clock.c arch/arm/include/asm/arch-mx6/crm_regs.h include/configs/mx6_common.h
generated by cgit v1.1 at 2024-11-09 14:04:34 +0000