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* add: reading special purpose registersMichal Simek2007-05-08-23/+41
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* add: Microblaze V5 exception handlingMichal Simek2007-05-08-2/+17
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* add: FSL control read and writeMichal Simek2007-05-08-72/+210
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* Merge git://www.denx.de/git/u-bootMichal Simek2007-05-08-9449/+50773
|\ | | | | | | | | | | | | Conflicts: include/asm-microblaze/microblaze_intc.h include/linux/stat.h
| * 5xxx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-05-05-0/+4
| | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
| * [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot messageGrzegorz Wianecki2007-05-05-6/+14
| | | | | | | | | | | | | | | | | | | | MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [PATCH] simplify silent consoleLadislav Michl2007-05-05-40/+6
| | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Stefan Roese <sr@denx.de>
| * [PATCH] Avoid assigning PCI resources from zero addressSergei Shtylyov2007-05-05-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE core complains and IDE drivers fails to work. Also, assigning zero to a BAR was illegal according to PCI 2.1 (the later revisions seem to have excluded the sentence about "0" being considered an invalid address) -- so, use a reasonable starting value of 0x1000 (that's what the most Linux archs are using). Alternatively, one might have fixed the calls to pci_set_region() individually (some code even seems to have taken care of this issue) but that would have been a lot more work. :-) Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Stefan Roese <sr@denx.de>
| * [patch] setenv(...) can delete environmentalvariablesJeffrey Mann2007-05-05-1/+4
| | | | | | | | | | | | | | | | update setenv() function so that entering a NULL value for the variable's value will delete the environmental variable Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Acked-by: Stefan Roese <sr@denx.de>
| * [patch] use unsigned char in smc91111 driver for macMike Frysinger2007-05-05-4/+4
| | | | | | | | | | | | | | | | | | the v_mac variable in the smc91111 driver is declared as a signed char ... this causes problems when one of the bytes in the MAC is "signed" like 0xE0 because when it gets printed out, you get a display like: 0xFFFFFFE0 and that's no good Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Coding stylke cleanup; update CHANGELOG.Wolfgang Denk2007-05-05-26/+87
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-05-05-171/+55
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| | * Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-05-05-5/+1392
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| | * | ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHzJeffrey Mann2007-05-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese2007-05-05-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-29-3191/+9483
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| | * \ \ Merge with /home/stefan/git/u-boot/u-boot-ppc4xxStefan Roese2007-04-29-9/+21
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| | | * | | ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.Matthias Fuchs2007-04-24-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| | * | | | ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driverStefan Roese2007-04-29-154/+8
| | |/ / / | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Fix chip select timing for SysACE access on AMCC KatmaiStefan Roese2007-04-19-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous versions used full wait states for the chip select #1 which is connected to the Xilinix SystemACE controller on the AMCC Katmai evaluation board. This leads to really slow access and therefore low performance. This patch now sets up the chip select a lot faster resulting in much better read/write performance of the Linux driver. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Add STX GP3 SSA board to MAKEALL script; update CHANGELOG.Wolfgang Denk2007-05-05-1/+270
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xxWolfgang Denk2007-05-05-148/+3085
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| | * | | | Cleaned up some 85xx PCI bugsAndy Fleming2007-05-02-19/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Add support for the 8568 MDS boardAndy Fleming2007-05-02-2/+1495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Add support for treating unknown PHYs as generic PHYs.David Updegraff2007-05-02-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When bringing up u-boot on new boards, PHY support sometimes gets neglected. Most PHYs don't really need any special support, though. By adding a generic entry that always matches if nothing else does, we can provide support for "unsupported" PHYs for the tsec. The generic PHY driver supports most PHYs, including gigabit. Signed-off-by: David Updegraff <dave@cray.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Reworked 85xx speed detection codeAndy Fleming2007-04-23-36/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed the code to read the registers and calculate the clock rates, rather than using a "switch" statement. Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Enable 8544 supportAndy Fleming2007-04-23-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add support to the Makefile * Add 8544 configuration support to the tsec driver * Add 8544 SVR numbers to processor.h Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
| | * | | | Support 1G size on 8548Andy Fleming2007-04-23-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nGAndy Fleming2007-04-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Only set ddrioovcr for 8548 rev1.Andy Fleming2007-04-23-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | Tweak DDR ECC error counterAndy Fleming2007-04-23-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | | 85xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-04-23-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi <timur@freescale.com>
| | * | | | Some 85xx cpu cleanupsAndy Fleming2007-04-23-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Cleaned up the TSR[WIS] clearing * Cleaned up DMA initialization Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| | * | | | Add cpu support for the 8544Andy Fleming2007-04-23-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recognize new SVR values, and add a few register definitions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| | * | | | Add MPC8544DS basic port board files.Jon Loeliger2007-04-23-0/+686
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board port under new board/freescale directory structure and reuse existing PIXIS FPGA support there. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
| | * | | | Add MPC8544DS main configuration file.Jon Loeliger2007-04-23-0/+591
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
| | * | | | Fix PCI I/O space mapping on Freescale MPC85x0ADSSergei Shtylyov2007-04-23-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-)
| | * | | | u-boot: Fix e500 v2 core reset bugZang Roy-r619112007-04-23-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | | | u-boot: v2: Remove the fixed TLB and LAW entrynubmerZang Roy-r619112007-04-23-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | | | u-boot: Fix the 85xxcds tsec bugZang Roy-r619112007-04-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the 85xxcds tsec bug. When enable PCI, tsec.o should be added to u-boot.lds to make tsec work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | | | u-boot: Fix CPU2 errata on MPC8548CDS boardZang Roy-r619112007-04-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch apply workaround of CPU2 errata on MPC8548CDS board. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
| | * | | | u-boot: Disables MPC8548CDS 2T_TIMING for DDR by defaultebony.zhu@freescale.com2007-04-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
| | * | | | u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS boardZang Roy-r619112007-04-23-40/+67
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | | Make "file" command happy with some config.mk files; update CHANGELOGWolfgang Denk2007-05-05-0/+111
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| * | | | Merge with /home/wd/git/u-boot/custodian/u-boot-nand-flashWolfgang Denk2007-05-05-21/+10
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| | * \ \ \ Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-05-05-5/+1392
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| | * | | | NAND: Wrong calculation of page number in nand_block_bad()Thomas Knobloch2007-05-05-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case that there is no memory based bad block table available the function nand_block_checkbad() in drivers/mtd/nand/nand_base.c will call nand_block_bad() directly. When parameter 'getchip' is set to zero, nand_block_bad() will not right shift the offset to calculate the correct page number. Signed-off-by: Thomas Knobloch <knobloch@siemens.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-23-37/+77
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| | * | | | Remove BOARDLIBS usage completelyStefan Roese2007-04-23-22/+5
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-05-05-31/+82
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