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* powerpc/8xxx: Fix in USB device-tree fixupramneek mehresh2014-09-24-11/+9
| | | | | | | | | | | | | | | | Fix following issues in USB device-tree fixup: - returns when either dr_mode or phy_type not defined. This was terminating fix-up when only either property was defined in hwconfig string - updates dr_mode_type or dr_phy_type with junk value when their index is -1. Now these are updated only when their respective index is pointing to relevant types in modes[] and phys[] array - dr_mode_type and dr_phy_type were not NULL for each controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Add T1042RDB board supportvijay rai2014-09-24-10/+39
| | | | | | | | | | | | | | | | | | | | | | | | T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-bootvijay rai2014-09-24-4/+14
| | | | | | | | | | | | This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-09-23-7/+11
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| * dm: avoid dev->req_seq overflowRobert Baldyga2014-09-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Since dev->req_seq value is initialized from "reg" property of fdt node, there is posibility, that address value contained in fdt is greater than INT_MAX, and then value in dev->req_seq is negative which led to probe() fail. This patch fix this problem by ensuring that req_seq is positive, unless it's one of errno codes. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: serial: Don't require device tree to configure a consoleSimon Glass2014-09-23-1/+2
| | | | | | | | | | | | Allow serial_find_console_or_panic() to work without a device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Allow device_bind() to used without CONFIG_OF_CONTROLSimon Glass2014-09-23-2/+5
| | | | | | | | | | | | | | | | The sequence number support in driver model requires device tree control. It should be skipped if CONFIG_OF_CONTROL is not defined, and should not require functions from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sf: Add an empty entry to the parameter listSimon Glass2014-09-23-0/+1
| | | | | | | | | | | | | | | | The list is supposed to be terminated with a NULL name, but is not. If a board probes a chip which does not appear in the table, U-Boot will crash (at least on sandbox). Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Fix repeated comment in READMESimon Glass2014-09-23-4/+1
| | | | | | | | | | | | A merge error ended up repeating a similar sentence twice. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'misc' of git://git.denx.de/u-boot-x86Tom Rini2014-09-23-12/+19
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| * patman: Add a -m option to avoid copying the maintainersSimon Glass2014-09-21-5/+12
| | | | | | | | | | | | | | | | | | The get_maintainers script is a useful default, but sometimes is copies too many people, or takes a long time to run. Add an option to disable it and update the README. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Fix the logic for the bloat commandSimon Glass2014-09-21-3/+3
| | | | | | | | | | | | | | This check should now be done whatever mode buildman is running in, since we may be displaying information while building. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Update minor documentation changesJagannadha Sutradharudu Teki2014-09-21-4/+4
| | | | | | | | | | | | | | | | - Use _defconfig instead of _config, but still _config is working. - Corrected README.sandbox path in ./README Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-21-13/+102
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| * | am335x_evm: Add boot script support to am335x_evmGuillaume GARDET2014-09-17-11/+18
| | | | | | | | | | | | | | | | | | | | | This patch adds boot script support to am335x_evm Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@ti.com>
| * | OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' ↵Guillaume GARDET2014-09-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'. This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards. This allows to use EXT partition instead of FAT, while keeping FAT compatibility. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@ti.com>
| * | ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri2014-09-17-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | ARM: at91sam9rlek: convert to generic board supportWu, Josh2014-09-19-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: at91sam9n12ek: convert to generic board supportWu, Josh2014-09-19-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCBoris BREZILLON2014-09-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | USB: ehci-atmel: use pcr to enable or disable clockBo Shen2014-09-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | USB: ohci-at91: use pcr to enable or disable clockBo Shen2014-09-19-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: add pcr related definitionBo Shen2014-09-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Using CPU_HAS_PCR micro to present the SoC has pcr (peripheral control register). Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: use pcr to enable or disable peripheral clockBo Shen2014-09-19-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: sama5d3: add timings registerBo Shen2014-09-19-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: sama5d3xek: enable NOR flash supportBo Shen2014-09-19-1/+12
| | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: sama5d3xek: add nor flash init functionBo Shen2014-09-19-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add NOR flash hardware init function, including SMC and PIO configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh2014-09-19-10/+14
| |/ |/| | | | | | | | | | | | | | | | | We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | kconfiglib: change SPDX-License-Identifier to ISCMasahiro Yamada2014-09-17-1/+1
| | | | | | | | | | | | | | | | | | Commit f219e01311b2 (tools: Import Kconfiglib) added SPDX GPL-2.0+ to this library by mistake. It should be ISC. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ulf Magnusson <ulfalizer@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-280/+2140
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-17-280/+2140
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| | * imx: mx6slevk: Change to use generic boardYe.Li2014-09-11-0/+2
| | | | | | | | | | | | | | | | | | Enable CONFIG_SYS_GENERIC_BOARD for imx6slevk to use generic board. Signed-off-by: Ye.Li <B37916@freescale.com>
| | * imx: mx6q/dlarm2: Change to use generic boardYe.Li2014-09-11-0/+2
| | | | | | | | | | | | | | | | | | | | | Enable the CONFIG_SYS_GENERIC_BOARD for imx6q/dl arm2 board to use generic board. Signed-off-by: Ye.Li <B37916@freescale.com>
| | * README.imximage: Fix the maximum DCD sizeFabio Estevam2014-09-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 021e79c85371 ("tools: imximage: Fix the maximum DCD size for mx53/mx6") we have fixed the maximum DCD size for mx53/mx53. Do the same on the README document for consistency. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * imx: Fix build of mx6sxsabresdStefano Babic2014-09-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 224beb833e544b802f08765271cec07667d39669 add clock enabling function for FEC, but the masks are not available for SX processor and the mx6sxsabresd cannot be built clean. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Nikita Kiryanov <nikita@compulab.co.il>
| | * mx6sxsabresd: Add PCI supportFabio Estevam2014-09-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested with an Intel Wireless PCI 7260HMW card: U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11) CPU: Freescale i.MX6SX rev1.0 at 792 MHz Reset cause: WDOG Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-8/+58
| | | | | | | | | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | | | | | | | | | | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6qsabreauto: Remove imx6q-sabreauto.dtsFabio Estevam2014-09-09-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced 'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains the 'model' and 'compatible' strings. After this commit the final binary is also changed from 'u-boot.imx' to 'u-boot-dtb.imx', which may confuse users. So revert it until a more complete and useful device tree could be provided. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * imx: nitrogen6x: Replace 'fatload' by 'load' command in env settings to be ↵Guillaume GARDET2014-09-09-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | filesystem independent nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic 'load' command instead of 'fatload'. It allows to use ext filesystem and keep compatibilty with fat filesystem. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Stefano Babic <sbabic@denx.de> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx6dlsabresd: Use its own DCD tableFabio Estevam2014-09-09-1/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently mx6dlsabresd shares the same DCD settings with the nitrogen board. Provide a DCD configuration file specific to mx6dlsabresd with the settings recommended by the Freescale hardware team. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
| | * arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-09-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
| | * mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-09-4/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * imximage: Fix imximage IVT bug for EIM-NOR bootYe.Li2014-09-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The load region size of EIM-NOR are defined to 0. For this case, the parameter "imximage_init_loadsize" must be calculated. The imximage tool implements the calculation in the "imximage_generate" function, but the following function "imximage_set_header" resets the value and not calculate. This bug cause some fields of IVT head are not correct, for example the boot_data and DCD overlay the application area. Signed-off-by: Ye.Li <B37916@freescale.com>
| | * iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
| | * imx: ventana: Avoid undefined behaviourThierry Reding2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
| | * tools: imximage: Fix the maximum DCD size for mx53/mx6Fabio Estevam2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to mx53 and mx6 reference manuals: "The maximum size of the DCD limited to 1768 bytes." As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and excluding the first entry, which is the header leads to 220 as the maximum number for DCD size. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
| | * imx: ventana: add pci fixup for PLX PEX860x switch GPIOTim Harvey2014-09-09-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion. These boards use GPIO on the PLX device as PERST# for the downstream ports thus we assert this when the PLX is enumerated. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-09-0/+11
| | | | | | | | | | | | | | | | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
generated by cgit v1.1 at 2024-11-19 18:17:03 +0000