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* ARM: sunxi: Add support for R_PIO gpio banksHans de Goede2014-10-24-2/+29
| | | | | | | | | | | | | | | The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add basic A23 supportChen-Yu Tsai2014-10-24-3/+35
| | | | | | | | | | | The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup. There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-2/+2
| | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add support for uart0 on port F (mmc0)Chen-Yu Tsai2014-10-24-1/+12
| | | | | | | | | Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add sun8i (A23) UART0 pin mux supportChen-Yu Tsai2014-10-24-0/+6
| | | | | | | UART0 pin muxes on the A23 have a different function value. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Fix reset command on sun6i/sun8iChen-Yu Tsai2014-10-24-0/+30
| | | | | | | | | | The watchdog on sun6i/sun8i has a different layout. Add the new layout and fix up the setup functions so that reset works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> [ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
* ARM: sunxi: Add sun6i/sun8i timer block register definitionChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | The RTC hardware has been moved out of the timer block on sun6i/sun8i. In addition, there are more watchdogs available. Also note that the timer block definition is not completely accurate for sun5i/sun7i. Various blocks are missing or have been moved out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Move watchdog register definitions to separate fileChen-Yu Tsai2014-10-24-14/+27
| | | | | | | | | | | | On later Allwinner SoCs, the watchdog hardware is by all means a separate hardware block, with its own address range and interrupt line. Move the register definitions to a separate file to facilitate supporting newer SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Fix build break when CONFIG_MMC is not definedChen-Yu Tsai2014-10-24-1/+7
| | | | | | | | | | | | BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI. This is used when we want to use uart0 from port F, which conflicts with mmc0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add CONFIG_MACH_TYPE defines to sun4i, sun5i and sun7iHans de Goede2014-10-24-0/+3
| | | | | | | | | | | | | Many people are still using old linux-sunxi-3.4 kernels on sunxi devices, adding the proper MACH_TYPE defines for this allows people to switch to upstream u-boot, so that we can stop maintaining the linux-sunxi u-boot fork. These machine-ids are all properly registered at: http://www.arm.linux.org.uk/developer/machines/ Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Kconfig: Unify sunxi Kconfig codeHans de Goede2014-10-24-27/+5
| | | | | | | | Unify the sunxi Kconfig code, instead of having separate code blocks for each of sun4i - sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Enable second sdcard slot found on some boardsHans de Goede2014-10-24-0/+8
| | | | | | | | | | | | | | Enable the second sdcard slot found on some boards. Note that we do not set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful, Except for on the Mele-M3 where the second sdcard is an eMMC, from which the device can also boot, and there we want to have both in the SPL, so that a single u-boot binary can both from both. So for the M3 we do prefix the defconfig setting with the special "+S:" syntax so that it applies to the SPL too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Use PG3 - PG8 as io-pins for mmc1Hans de Goede2014-10-24-3/+5
| | | | | | | | | | None of the known sunxi devices actually use mmc1 routed through PH, where as some devices do actually use mmc1 routed through PG, so change the routing of mmc1 to PG. If in the future we encounter devices with mmc1 routed through PH, we will need to change things to be a bit more flexible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: When we've both mmc0 and mmc2, detect from which one we're bootingHans de Goede2014-10-24-8/+31
| | | | | | | | | | | | | sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're booting, and make that one "mmc dev 0" so that a single u-boot binary can be used for both the onboard eMMC and for external sdcards. When we're booting from mmc2, we make it dev 0 because that is where the SPL will load the tertiary payload (the actual u-boot binary in our case) from, see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Turn MMC_SUNXI_SLOT_EXTRA into a proper Kconfig optionHans de Goede2014-10-24-1/+9
| | | | | | | | | Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL check is not necessary with Kconfig, because only options explicitly marked as also being for the SPL get set during SPL builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add mmc card-detect functionalityHans de Goede2014-10-24-0/+48
| | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Add Colombus board defconfigChen-Yu Tsai2014-10-24-0/+9
| | | | | | | | | | | | | The Colombus board is an A31 evaluation board from WITS Technology. Maxime has kindly agreed to maintain this board. [1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.html Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add basic A31 supportMaxime Ripard2014-10-24-1/+40
| | | | | | | | | | | Add a new sun6i machine that supports UART and MMC. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef around mmc and smp code, drop MACH_TYPE] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Setup the A31 UART0 muxingMaxime Ripard2014-10-24-0/+4
| | | | | | | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens@csie.org: reorder #ifs by SUN?I] [wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Define UART0 pins for A31Chen-Yu Tsai2014-10-24-0/+3
| | | | | | | UART0 is the default debug/console UART on the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi-mmc: Add mmc support for sun6i / A31Hans de Goede2014-10-24-5/+11
| | | | | | | | | | | The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use setbits_le32 for reset control, drop obsolete changes, rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Add clock supportChen-Yu Tsai2014-10-24-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. This includes changes from the following commits from u-boot-sunxi: a92051b ARM: sunxi: Add sun6i clock controller structure 1f72c6f ARM: sun6i: Setup the UART0 clocks 5f2e712 ARM: sunxi: Enable pll6 by default on all models 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31 12e1633 ARM: sun6i: Add initial clock setup for SPL 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup. 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6} c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: styling fixes reported by checkpatch.pl] [wens@csie.org: drop unsupported SPL code block and unused gpio.h header] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Add support for the power reset control module found on the A31Oliver Schinagl2014-10-24-0/+272
| | | | | | | | | | | | | | | | | | | The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block modules, and also PLL biasing in the main clock module. This patch adds the register definitions, and also enables the clocks and resets for the RTC block PIO (pin controller) and P2WI (push-pull 2 wire interface) which is used to talk to the PMIC. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: spacing fixes reported by checkpatch.pl] [wens@csie.org: Use setbits helper in PRCM init function] [wens@csie.org: rephrase commit message to explain what the hardware supports and what we actually enable] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Add base address for the new controllers in A31Oliver Schinagl2014-10-24-0/+9
| | | | | | | | | A31 has several new and changed memory address. This patch adds them. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not definedChen-Yu Tsai2014-10-24-1/+7
| | | | | | | | | BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Use macro values for setting UART GPIO pull-upsChen-Yu Tsai2014-10-24-3/+3
| | | | | | | | | We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add support for the Mele M3 boardHans de Goede2014-10-24-0/+7
| | | | | | | | | | | | | The Mele M3 is yet another Allwinnner based Android top set box from Mele. It uses a housing similar to the A2000, but without the USM sata storage slot at the top. It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices), 100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: sunxi: add SDHC support for sun6i/sun7i/sun8iWills Wang2014-10-24-0/+3
| | | | | | | Allwinner A20/A23/A31's SD/MMC host support SDHC High Capacity feature. Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sun7i: Add support for Olimex A20-OLinuXino-LIME2Iain Paton2014-10-24-0/+43
| | | | | | | | | | This adds support for the Olimex A20-OLinuXino-Lime2 https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2 Differences to previous Lime boards are 1GB RAM and gigabit ethernet Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* kbuild: clear VENDOR variable to fix build error on tcshMasahiro Yamada2014-10-23-0/+2
| | | | | | | | | | | | | | | | | | | | Since the environment "VENDOR" is set in tcsh, it must be cleared in our makefile. Otherwise, boards without CONFIG_SYS_VENDOR fail to build: > make CROSS_COMPILE=arm-linux-gnueabi- wandboard_quad_defconfig all [ snip ] AR arch/arm/lib/lib.a CC arch/arm/lib/eabi_compat.o scripts/Makefile.build:55: /home/foo/u-boot/board/unknown/wandboard/ \ Makefile: No such file or directory make[2]: *** No rule to make target `/home/foo/u-boot/board/unknown/ \ wandboard/Makefile'. Stop. make[1]: *** [board/unknown/wandboard] Error 2 make: *** [__build_one_by_one] Error 2 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: Tom Everett <tom@khubla.com> Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2014-10-23-63/+1014
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| * tegra: apalis_t30: master revampMarcel Ziswiler2014-10-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Apalis T30 as per the following commits c369139234c03b1494394d12cd27009f47aa6606 tegra: dts: Add serial port details 461be2f96e4b87e5065208c6659a47dd0ad9e9f8 kconfig: remove redundant "string" type in arch and board Kconfigs f1ef2b62339526df3b921bcfefd174ce76d4c624 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: dts: colibri_t30 add serial port detailsMarcel Ziswiler2014-10-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | Add missing chosen stdout-path device tree node. This got missed by commit c369139234c03b1494394d12cd27009f47aa6606 tegra: dts: Add serial port details Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: colibri_t30: clean-up spurious new lineMarcel Ziswiler2014-10-22-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Clean-up a spurious new line which got introduced resp. left behind by commit f1ef2b62339526df3b921bcfefd174ce76d4c624 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Use mem size from MC in combination with get_ram_size()Marcel Ziswiler2014-10-22-51/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On popular request this now completes the Warren's work started for TK1: aeb3fcb35956461077804720b8a252d50758d7e0 ARM: tegra: Use mem size from MC rather than ODMDATA In addition to the move of using the Tegra memory controller (MC) register rather than ODMDATA for T20, T30 and T114 as well it further uses the generic get_ram_size() function (see "common/memsize.c") <supposed to be used in each and every U-Boot port>TM. Added benefit is that it should <catch 99% of hardware related (i. e. reliably reproducible) memory errors> as well. Thoroughly tested on the various Toradex line of Tegra modules available which unfortunately does not include T114 and T124 (yet at least) plus on the Jetson TK1. Based-on-work-by: Stephen Warren <swarren@nvidia.com> Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: clean-up useless defineMarcel Ziswiler2014-10-22-4/+0
| | | | | | | | | | | | | | | | | | | | | | Wondering what exactly that one should bring (;-p). Looks like a remnant of the last commit 783e6a72b8278d59854ced41a4696c9a14abbb0b kconfig: move CONFIG_OF_* to Kconfig Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * gpio: header file comment spelling fixesMarcel Ziswiler2014-10-22-5/+5
| | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: colibri_t30: asix usb ethernet reset regressionMarcel Ziswiler2014-10-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ASIX USB to Ethernet reset which due to the new driver model Tegra GPIO driver changes now requires a label string to be provided otherwise the reservation and subsequent direction/value calls will fail. This fixes a regression introduced by commit: 2fccd2d96badcdf6165658a99771a4c475586279 tegra: Convert tegra GPIO driver to use driver model Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: gpio: fix null label regressionMarcel Ziswiler2014-10-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix Tegra GPIO driver to not crash resp. misbehave upon requesting GPIOs with an empty aka NULL label. As the driver uses exclusively the label to check for reservation status actually supplying one is mandatory! This fixes a regression introduced by commit: 2fccd2d96badcdf6165658a99771a4c475586279 tegra: Convert tegra GPIO driver to use driver model Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * mmc: Tegra: Fix timeout issue seen on certain eMMC partsMarcel Ziswiler2014-10-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During rigorous testing of our latest update infrastructure I came across quite consistent timeouts on certain eMMC parts (e.g. Hynix H26M21001ECR) when writing big (e.g. in excess of 400 MB) file system images: MMC write: dev # 0, block # 40960, count 944128 ... mmc_send_cmd_bounced: MMC Timeout Interrupt status 0x00000001 Interrupt status enable 0xdfff003b Interrupt signal enable 0xdfff0002 Present status 0x01870106 mmc write failed Comparing the various data sheets I came across the following timeout specification: Secure Erase/TRIM Timeout=300ms*2*10=6000ms Unfortunately empirical testing still failed albeit much more rarely. Increasing the timeout to 8000ms made it finally disappear entirely. This patch allows us writing various eMMC parts without seeing any further issues. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: tegra: use architecture specific memcpyMarcel Ziswiler2014-10-22-0/+2
| | | | | | | | | | | | | | | | Use architecture specific memcpy to speed up things. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: tegra: initial support for apalis t30Marcel Ziswiler2014-10-22-0/+866
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds board support for the Toradex Apalis T30 a computer on module which can be used on different carrier boards. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot and environment storage - Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210 fixes hit mainline) - MMC/SD cards (both 8-bit as well as 4-bit slot) - USB client/host (dual role port as client e.g. for DFU/UMS, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tablesStephen Warren2014-10-22-0/+5
| | | | | | | | | | | | | | | | | | | | This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | mips: enable CONFIG_USE_PRIVATE_LIBGCC by defaultMasahiro Yamada2014-10-23-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without the private libgcc, we need a full multilib toolchain with different libgcc or multiple toolchains to build all BE/LE and hard-float/soft-float variants of MIPS boards. That is not feasible. This commit allows us to build all the MIPS boards with a single kernel.org toolchain: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_mips-linux.tar.xz This change sounds reasonable for most users. If necessary, you can disable this option via "make menuconfig" or friends. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | kconfig: invoke silentoldconfig if spl, tpl/.config is updatedMasahiro Yamada2014-10-23-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | When spl/.config is updated by "make spl/menuconfig" or friends, spl/include/config/auto.conf, spl/include/generated/autoconf.h and some other files must be updated by "make silentoldconfig". There is no hook for SPL in the top Makefile, so this commit touches .config when spl/.config is updated to invoke silentoldconfig. Likewise for TPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | kbuild: fix a bug of the u-boot-spl link ruleMasahiro Yamada2014-10-23-4/+4
| | | | | | | | | | | | | | | | | | | | cmd_u-boot-spl includes $(PLATFORM_LIBS) which changes when CONFIG_USE_PRIVATE_GCC is updated. The u-boot-spl image should be re-linked if any prerequisite is newer than it or the command line has changed. $(call, if_changed,...) should be used instead of $(call cmd,...). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | kconfig: move CONFIG_USE_PRIVATE_LIBGCC to KconfigMasahiro Yamada2014-10-23-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86. Those architectures should "select" HAVE_PRIVATE_LIBGCC and CONFIG_USE_PRIVATE_LIBGCC should depend on it. Currently, this option is enabled on Tegra boards and x86 architecture. Move the definition from header files to Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* | kbuild: drop CONFIG_USE_PRIVATE_LIBGCC=path/to/libgcc syntaxMasahiro Yamada2014-10-23-4/+0
| | | | | | | | | | | | | | | | | | Now CONFIG_USE_PRIVATE_LIBGCC is only used as a boolean macro. Remove CONFIG_USE_PRIVATE_LIBGCC=path/to/libgcc syntax. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: set CONFIG_USE_PRIVATE_LIBGCC to yMasahiro Yamada2014-10-23-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation of this commit is to change CONFIG_USE_PRIVATE_LIBGCC to a boolean macro so we can move it to Kconfig. In the current implementation, there are two forms of syntax for this macro: - CONFIG_USE_PRIVATE_LIBGCC=y - CONFIG_USE_PRIVATE_LIBGCC=path/to/private/libgcc The latter is only used by x86 architecture. With a little bit refactoring, it can be converted to the former. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: move CONFIG_SYS_HZ to lib/KconfigMasahiro Yamada2014-10-23-25/+8
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_HZ is always defined as 1000 in config_fallbacks.h (but some boards still have redundant definitions). This commit moves the definition and the document in README to Kconfig. Since lib/Kconfig can assure that CONFIG_SYS_HZ is 1000, the sanity check in lib/time.c should be removed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-11-12 19:51:20 +0000