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* Exynos5420: Add base patch for SMDK5420Rajeshwari Birje2013-12-30-1/+229
| | | | | | | | | | | Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-16/+390
| | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-58/+484
| | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1679
| | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-30-0/+167
| | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-30-0/+837
| | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-30-1/+48
| | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-527/+437
| | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: AM43xx: Add MaintainerLokesh Vutla2013-12-18-1/+1
| | | | | | Adding Maintainer for AM43xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-19/+136
| | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-3/+256
| | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-26/+134
| | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-17/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-2/+65
| | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Select clk source for Timer2Lokesh Vutla2013-12-18-0/+4
| | | | | | Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG supportSekhar Nori2013-12-18-0/+16
| | | | | | | | | CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+87
| | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Add extra ENV settingsLokesh Vutla2013-12-18-0/+63
| | | | | | | Add Extra env settings. This is derived from am335x Extra ENV settings. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Add L2 SupportLokesh Vutla2013-12-18-0/+5
| | | | | | AM4372 uses PL310 L2 Cache. Enable the configs for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-104/+29
| | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)Stefan Roese2013-12-18-0/+3
| | | | | | | | | | | | | Patch f33b9bd3 [arm: omap3: Enable clocks for peripherals only if they are used] breaks SPL booting on Beagleboard. Since some gpio input's are read to detect the board revision. But with this patch above, the clocks to the GPIO subsystems are not enabled per default any more. The GPIO banks need to be configured specifically now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Michael Trimarchi <michael@amarulasolutions.com>
* Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-61/+54
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| * ARM: pxa: Fix CONFIG_SYS_HZ on PXAMarek Vasut2013-12-18-23/+23
| | | | | | | | | | | | | | | | | | The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across U-Boot. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * arm: pxa: init ethaddr for LP-8x4x using DTSergei Ianovich2013-12-18-17/+0
| | | | | | | | | | | | | | | | | | | | | | When DT define aliases for etherner0 and ethernet1, U-Boot automatically patched MAC addresses using ethaddr and eth1addr environment variables respectively. Custom initialization is no longer needed. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * arm: pxa: update LP-8x4x to boot DT kernelSergei Ianovich2013-12-18-5/+5
| | | | | | | | | | | | | | | | DT kernel requires CONFIG_OF_LIBFDT. 'bootm' needs to know DT location. In addition, fix kernel console device and enable U-Boot long help. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * arm: pxa: fix 2nd flash chip address on LP-8x4xSergei Ianovich2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Initial configuration has worng address of the second chip. There is an alias for the 1st chip at 0x02000000 in earlier verions of LP-8x4x, so the boot normally. However, new LP-8x4xs have a bigger 1st flash chip, and hang on boot without this patch. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * arm: pxa: fix LP-8x4x USB supportSergei Ianovich2013-12-18-16/+25
| | | | | | | | | | Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * ARM: pxa: prevent PXA270 occasional reboot freezesSergei Ianovich2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
* | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-31/+735
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| * | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add the Tamonten™ NG Evaluation Carrier boardAlban Bedel2013-12-18-0/+654
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new Tamonten™ NG platform from Avionic Design. Currently only I2C, MMC, USB and ethernet have been tested. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | i2c: tegra: Add the fifth bus on SoC with more than 4 busesAlban Bedel2013-12-18-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: config: USB: Tegra30/114: Fix EHCI timeout issue on "bootp"Jim Lin2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the timeout issue after running "bootp" command in u-boot console. For example you see "EHCI timed out on TD- token=0x...". TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a controller reset and before RUN bit is set (per technical reference manual). Signed-off-by: Jim Lin <jilin@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: allow build to succeed with SPL disabledVidya Sagar2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot-dtb-tegra.bin and u-boot-nodtb-tegra.bin binaries are generated only if the SPL build is enabled as they have dependency on SPL build Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Change maintainer for Avionic Design boardsThierry Reding2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | I no longer work for Avionic Design and don't have access to hardware, so I'll pass on maintainership to Alban. Acked-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Do not program CPCON field for PLLXThierry Reding2013-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Fix PLLX M, N, P init settingsJimmy Zhang2013-12-18-24/+59
| |/ | | | | | | | | | | | | | | | | | | | | | | The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-17/+269
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| * | arm: koelsch: Add support reset functionNobuhiro Iwamatsu2013-12-18-0/+8
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: koelsch: Add support I2CNobuhiro Iwamatsu2013-12-18-0/+16
| | | | | | | | | | | | | | | | | | This supports sh_i2c on koelsch board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: koelsch: Add support EthernetNobuhiro Iwamatsu2013-12-18-2/+98
| | | | | | | | | | | | | | | | | | | | | The koelsch board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: lager: Add support reset functionNobuhiro Iwamatsu2013-12-18-0/+10
| | | | | | | | | | | | | | | | | | The lager board uses I2C for reset. ned-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: lager: Add support I2CNobuhiro Iwamatsu2013-12-18-0/+14
| | | | | | | | | | | | | | | | | | | | | The lager board has I2C for rcar. This supports I2C for rcar on lager board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: lager: Add support EthernetNobuhiro Iwamatsu2013-12-18-0/+89
| | | | | | | | | | | | | | | | | | | | | The lager board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: rmobile: Update README.rmobileNobuhiro Iwamatsu2013-12-18-15/+34
| |/ | | | | | | | | | | | | Add infomation of Lager and Koelsh board, and R-Car. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper positionBo Shen2013-12-17-5/+3
| | | | | | | | | | | | | | | | | | | | In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, move the CONFIG_SYS_NO_FLASH to proper position, then we don't need to undef these two commands. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: atmel: at91sam9x5: cleanup unneeded undefBo Shen2013-12-17-5/+0
| | | | | | | | | | | | | | remove unneeded #undef for at91sam9x5ek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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