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| | * | | | | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | | ppc4xx: Change Luan config file to support ECCStefan Roese2007-06-01-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the updated 44x DDR2 driver the Luan board now supports ECC generation and checking. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-06-01-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | Merge with /home/wd/git/u-boot/stx-gp3ssaWolfgang Denk2007-05-31-21/+35
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| | * | | | | Add support for STX GP3SSA (stxssa) Board with 4 MiB flash.Wolfgang Denk2007-05-31-21/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-04-126/+245
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| * | | | | | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-05-28-91/+190
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| | * | | | | | Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH.Bartlomiej Sieka2007-05-27-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Add support for redundant environment.Bartlomiej Sieka2007-05-27-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable redundant environment, add a MTD partition for it; also add env. variable command for passing MTD partitions to the kernel command line. Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Change maximum console buffer size from 256 to 1024 bytes.Bartlomiej Sieka2007-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow passing longer command line to the kernel - useful especially for passing MTD partition layout. Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Fix: Add missing NULL termination in strings expanded by macros parser.Bartlomiej Sieka2007-05-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Update EEPROM's page write bits and write delay.Bartlomiej Sieka2007-05-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A have a page write capability of two bytes", and "This device offers fast (1ms) byte write". Add 3ms of extra delay. Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | MPC5XXX, Motion-PRO: Fix PHY initialization problem.Bartlomiej Sieka2007-05-27-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Add support for the temperature sensor.Bartlomiej Sieka2007-05-27-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Add displaying of CPLD revision information during boot.Bartlomiej Sieka2007-05-27-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jan Wrobel <wrr@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | MPC5xxx: Change names of defines related to IPB and PCI clocks.Bartlomiej Sieka2007-05-27-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| | * | | | | | Motion-PRO: Add LED support.Bartlomiej Sieka2007-05-27-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jan Wrobel <wrr@semihalf.com> Signed-off-by: Marian Balakowicz <m8@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| * | | | | | | Merge with /home/stefan/git/u-boot/acadia-nandStefan Roese2007-05-24-27/+25
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| | * | | | | | | ppc4xx: Update AMCC Acadia support for board revision 1.1Stefan Roese2007-05-24-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Acadia (405EZ) support for the new 1.1 board revision. It also adds support for NAND FLASH via the 4xx NDFC. Please note that the jumper J7 must be in position 2-3 for this NAND support. Position 1-2 is for NAND booting only. NAND booting support will follow later. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | | | | ppc4xx: Use do { ... } while (0) for CPR & SDR access macrosStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | | | | ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | | | | ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | | | ppc4xx: Fix small 405EZ OCM initilization bug in start.SStefan Roese2007-05-24-1/+1
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As pointed out by Bruce Adler <bruce.adler@acm.org> this patch fixes a small bug in the 405EZ OCM initialization. Thanks for spotting. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-05-18-838/+2907
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| * | | | | | | [PATCH] Run new sequoia boards with an EBC speed of 83MHzJeffrey Mann2007-05-16-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
| * | | | | | | ppc4xx: Add mtcpr/mfcpr access macrosStefan Roese2007-05-11-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | | ppc4xx: Set bd->bi_pci_busfreq on 440EPx/GRx tooStefan Roese2007-05-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | | [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config fileJeffrey Mann2007-05-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A '3' got cut off in the formatting of the last patch to automatically change the clock speed of the system clock on sequoia board. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | | | [PATCH][NAND] Define the Vendor Id for Micron NAND FlashUlf Samuelsson2007-05-24-0/+2
| |/ / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ulf Samuelsson <ulf@atmel.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | | Fix compile problem cause my Microblaze mergeStefano Babic2007-05-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | | | | | Minor Coding Style cleanup, update CHANGELOG.Wolfgang Denk2007-05-16-24/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-05-16-75/+1686
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| * | | | | | | mpc83xx: fix trivial error in MAKEALLKim Phillips2007-05-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | | | | Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | | | | mpc83xx: replace elaborate boottime verbosity with 'clocks' commandKim Phillips2007-05-01-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and fix CPU: to align with Board: display text. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | | | | mpc83xx: minor fixups for 8313rdb introductionKim Phillips2007-04-25-17/+18
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| * | | | | | | mpc83xx: Add MPC8313ERDB support.Scott Wood2007-04-23-0/+1088
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Add generic PCI setup code.Scott Wood2007-04-23-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Add 831x support to speed.c.Scott Wood2007-04-23-26/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Add 831x support to global_data.hScott Wood2007-04-23-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().Scott Wood2007-04-23-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Recognize SPR values for MPC8311 and MPC8313.Scott Wood2007-04-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | mpc83xx: Add register definitions for MPC831x.Scott Wood2007-04-23-7/+301
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | | | Merge git://www.denx.de/git/u-bootKim Phillips2007-04-23-5537/+40454
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| * | | | | | | | Fix two bugs for MPC83xx DDR2 controller SPD InitXie Xiaobo2007-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
* | | | | | | | | Coding Style Cleanup, new CHANGELOGWolfgang Denk2007-05-16-3/+255
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* | | | | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-microblazeWolfgang Denk2007-05-16-280/+735
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| * | | | | | | | | add: reading special purpose registersMichal Simek2007-05-08-23/+41
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| * | | | | | | | | add: Microblaze V5 exception handlingMichal Simek2007-05-08-2/+17
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| * | | | | | | | | add: FSL control read and writeMichal Simek2007-05-08-72/+210
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