| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.
We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.
Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
Include fb.h in mxsfb.h.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
| |
Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB
for mx7d. So that the warm reset is disabled.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
| |
This config was missed when porting to 2015.04 u-boot.
Signed-off-by: Han Xu <b45815@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If no epdc pannel is plugged into mx6slevk board, no need to
do the elan init operation for each i2c init transfer which
will slow the i2c speed.
If epdc panned is plugged into mx6slevk board, all works as the
original patch: "b6ba68516b681a38025252bd0ef6a6ed3e8adfa0" -
"MLK-10215 Add elan init in i.MX6SL-EVK board"
This patch also fix a bug that setup_elan_pads should be called in
board_init, but not board_late_init where too late to setup_elan_pads.
And align pad property with linux kernel, value is 0x17000.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* Add mx7d_19x19_lpddr3_arm2 target board supprt
* Enable i2c, spinor, usb, usdhc, qspi, enet, uart
* Build targets
mx7d_19x19_lpddr3_arm2_defconfig
mx7d_19x19_lpddr3_arm2_eimnor_defconfig
- Set EIMNOR settings for Intel Sibley Asynchronous mode
- Set flash sector size for 256kb (erase block size)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
| |
The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
| |
This piece of code will never be compiled and used,
since we use pmic framework. So remove the code block.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
Use pmic framework to simplify code and make code clean.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
| |
Add android features booti, fastboot and recovery to i.MX6UL EVK board.
Since there is no user button on the board, we can't implement
the recovery by using button.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
| |
Correct USDHC Port Selection bits in bmode value for SD1 and SD2.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Since the NAND has two pins conflict with SD2, when NAND is enabled, we
must disable SD2. So the CONFIG_SYS_FSL_USDHC_NUM needs configure to 1
and should be moved to under defining CONFIG_SYS_USE_NAND.
New build target for NAND boot:
mx6ul_ddr3_arm2_nand_config
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
Correct the EIMNOR settings to non-mux mode and set the environment
variables configuration to FLASH when using WEIMNOR boot.
New target is added for build WEIMNOR boot u-boot:
mx6ul_ddr3_arm2_eimnor_config
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
| |
Add maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit fdc5bac6ae8b699924c4e84b86e38aa73f694827)
|
|
|
|
|
|
|
|
| |
This patch adds enable/disable hooks support for ldb_di[0/1] clocks
and enables/disables them when necessary.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 839a1da941be48baf27c9cb28939cc6b2030424a)
|
|
|
|
|
|
|
|
| |
The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock
relevant code be built only for them.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c0dc175a9780505ec8939bda5dda9c2ec549a7f0)
|
|
|
|
|
|
|
|
| |
Move CONFIG_IMX_THERMAL to mx6_common.h
Make CONFIG_MXC_OCOTP only depends on CONFIG_CMD_FUSE, since when
THERMAL is not implemented, we may use fuse.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
| |
Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.
Old Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse)
Where
Troom,cal = 25C and
Slope = 0.4297157 – (0.0015974 * Count room fuse)
New Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset
Where
Troom,cal = 25C and
Slope = 0.4445388 – (0.0016549 * Count room fuse)
Offset = 3.580661
"
According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add board code for mx6ul ddr3 arm2 board.
QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR
Add sd1, qspi and spinor boot support
DDR script is 1.02 version.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Add BSP codes to support modules on the board:
I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial
DDR version: 1.0
Build target: mx6ulevk_config
mx6ulevk_qspi1_config
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
|
| |
register
Add platform check to avoid to access the reserved register
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
i.MX6UL qspi controller also needs at least 16 bytes when writing.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
comment out GPIO6/7 for MX6UL
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
PAD_CTL_SPEED_LOW for mx6ul same with mx6sx.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
add i.MX6UL clock related settings/macros/apis
When using TFT43AB, its pixel size is 480x272 which needs a
slow pix clock. Without apply the test_div in PLL video, we can't
get the pix clock in the rate.
So change the LCDIF clock calculation to use the test_div.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
| |
I2C4 support for i.MX
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
| |
Remove PCIe, xPU power, PL310 L2 Cache for MX6UL.
Update FEC MAC address, WDOG settings, USDHC clock rate.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since the system counter driver will also be used by mx6ul, move
this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
| |
Update imx registers base address for i.MX6UL
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
| |
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for
choose.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime.
The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value
has been occupied by i.MX6D as a dummy CPU type.
So we also need change i.MX6D to a invalid value 0x67.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
|
|
|
|
|
|
| |
We should not rely on pfuze_common_init to set the voltage,
may be we should remove the voltage settings in pfuze_common_init.
This patch is to setting the voltages in power_init_board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise
we may encounter errors,
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update IPU QoS settings from 0x007f007f to 0x77177717
according to the SoC team's recommendation. This change
should be able to balance AXI ID0/2/3 priority and set
AXI ID1 priority relatively lower, which matches the way
we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs,
IDMAC27 and IDMAC28 respectively in kernel. The specific
priority values for each AXI ID are supposed to be picked
for the sake of an overall good system performance.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
|
|
|
|
|
|
|
|
|
|
| |
Remove the authentication size to be a fixed size, due to
recovery.img may be much bigger than the boot.img
Add signature size to boot or recovery image size, which is
added by boot_signer in android build process
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
(cherry picked from commit d59b24fefcd56d085c4010643ca9f6522a3cc58a)
|
|
|
|
|
|
|
|
| |
Update settings for PRE. Value for Saturation THR of PREx,
changed from 0x20 to 0x10 to make system more stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
|
|
|
|
|
|
|
|
| |
In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not
ipg clock, correct it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
HOLDTIME + 1 is the number of clk cycles the fec is holding the output.
Set the right hold time value when the MDC root clock is greater than
100Mhz.
The issue was reported on i.MX28 and is fixed by Uwe Kleine-König in kernel:
https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/
drivers/net/ethernet/freescale/fec_main.c?id=63c607321492c5efc7a31bc4ea734b877f8e7f87
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 0373a160e7f698064a6625e85f9120b6c81c1b61)
|
|
|
|
|
|
| |
Add epdc default configuration file.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
| |
Move VIDEO config to the front of EPDC
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
-Use the new pins' name for imx6dl.
-Change the read/write to registers by using register structure.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 66e7a93ff1e47d0e47627a984bcf2337db4f3bbf)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
board/freescale/mx6sabresd/mx6sabresd.c
Remove imx6dl part, since already fixed.
|
|
|
|
|
|
|
| |
Update pcie code to align with imx_v2014.04. Mainly add DEBUG
related stuff.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
| |
Merge hab_caam_clock_enable and hab_caam_clock_disable into
one function
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
|
|
|
|
|
|
| |
Enable thermal for mx7dsabresd board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since the following piece settings can not be in DCD table, we
add them in enable_ipu_clock.
"
setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator
setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator
setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0
setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1
setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2
setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3
setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0
setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1
setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2
setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE
"
CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h,
the settings sure will effect.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update to 1.05 ddr script, url:
http://compass.freescale.net/livelink/livelink?func=ll&
objId=233944823&objAction=browse&viewType=1
File name:
arik_r2_sabre_ddr3_528_1.05c.inc
Update:
Read latency
Aging control for IPU1/PRE0/PRE3
Aging control for IPU2/PRE1/PRE2
Test results:
3 boards passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
|