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* net: cosmetic: nfs.* checkpatch complianceJoe Hershberger2012-05-15-152/+150
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: cosmetic: net.c checkpatch complianceJoe Hershberger2012-05-15-15/+17
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: cosmetic: eth.c checkpatch complianceJoe Hershberger2012-05-15-35/+32
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: cosmetic: bootp.* checkpatch complianceJoe Hershberger2012-05-15-193/+203
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: cosmetic: net.h checkpatch complianceJoe Hershberger2012-05-15-56/+60
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: Remove volatile from net APIJoe Hershberger2012-05-15-42/+41
| | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2012-04-30-61/+52
|\ | | | | | | | | | | | | | | | | | | * 'agust@denx.de' of git://git.denx.de/u-boot-staging: lin_gadget: use common linux/compat.h linux/compat.h: rename from linux/mtd/compat.h lin_gadget: use common mdelay gunzip: rename z{alloc, free} to gz{alloc, free} fs/fat: align disk buffers on cache line to enable DMA and cache part_dos: align disk buffers on cache line to enable DMA and cache
| * lin_gadget: use common linux/compat.hMike Frysinger2012-04-30-16/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge our duplicate definitions with the common header. Also fix drivers/usb/gadget/s3c_udc_otg_xfer_dma.c to use min() instead of min_t() since we remove the latter from compat.h. Additionally use memalign() directly as the lin_gadget specific kmalloc() macro is removed from lin_gadget_compat.h by this patch. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * linux/compat.h: rename from linux/mtd/compat.hMike Frysinger2012-04-30-19/+19
| | | | | | | | | | | | This lets us use it in more places than just mtd code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * lin_gadget: use common mdelayMike Frysinger2012-04-30-1/+0
| | | | | | | | | | | | No need to provide our own mdelay() macro when we have a func for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * gunzip: rename z{alloc, free} to gz{alloc, free}Mike Frysinger2012-04-30-12/+9
| | | | | | | | | | | | | | This allows us to add a proper zalloc() func (one that does a zeroing alloc), and removes duplicate prototypes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * fs/fat: align disk buffers on cache line to enable DMA and cacheEric Nelson2012-04-30-10/+12
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * part_dos: align disk buffers on cache line to enable DMA and cacheEric Nelson2012-04-30-3/+3
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-04-30-301/+507
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
| * \ Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2012-04-30-301/+507
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
| | * | powerpc/ppc4xx: Remove typedefs for gdsys FPGADirk Eibach2012-04-30-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Fix typo in gdsys_fpga.hDirk Eibach2012-04-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Update gdsys board configurationsDirk Eibach2012-04-30-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20Dirk Eibach2012-04-30-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In hardware revision 1.20 one more fan controller is added to dlvision-10g. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changesDirk Eibach2012-04-30-37/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print fpga info at last_stage_init on gdsys 405ep boards. Use dtt_init() to startup fans. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Make gdsys 405ep boards reset more genericDirk Eibach2012-04-30-217/+366
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to add boards that have different hardware for fpga reset, any 405ep gdsys board now provides these functions: void gd405ep_init(void); void gd405ep_set_fpga_reset(unsigned state); void gd405ep_setup_hw(void); int gd405ep_get_fpga_done(unsigned fpga); Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | powerpc/ppc4xx: Adjust environment size on neoDirk Eibach2012-04-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Environment size on neo has to be 0x20000 for compatibilty reasons. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Allow for parallel builds and saved outputAndy Fleming2012-04-30-15/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MAKEALL script cleverly runs make with the appropriate options to use all of the cores on the system, but your average U-Boot build can't make much use of more than a few cores. If you happen to have a many-core server, your builds will leave most of the system idle. In order to make full use of such a system, we need to build multiple targets in parallel, and this requires directing make output into multiple directories. We add a BUILD_NBUILDS variable, which allows users to specify how many builds to run in parallel. When BUILD_NBUILDS is set greater than 1, we redefine BUILD_DIR for each build to be ${BUILD_DIR}/${target}. Also, we make "./build" the default BUILD_DIR when BUILD_NBUILDS is greater than 1. MAKEALL now tracks which builds are still running, and when one finishes, it starts a new build. Once each build finishes, we run "make tidy" on its directory, to reduce the footprint. As a result, we are left with a build directory with all of the built targets still there for use, which means anyone who wanted to use MAKEALL as part of a test harness can now do so. Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-04-30-261/+1047
|\ \ \ \ | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot cmd_bdinfo: display the address map size (32-bit vs. 36-bit) PowerPC: correct the SATA for p1/p2 rdb-pc platform powerpc/corenet_ds: Slave core in holdoff when boot from SRIO powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO powerpc/corenet_ds: Slave uploads ucode when boot from SRIO powerpc/corenet_ds: Slave module for boot from SRIO powerpc/corenet_ds: Master module for boot from SRIO powerpc/corenet_ds: Document for the boot from SRIO powerpc/corenet_ds: Correct the compilation errors about ENV powerpc/srio: Rewrite the struct ccsr_rio powerpc/85xx:Fix lds for nand boot debug info powerpc/p2041rdb: add env in NAND support powerpc/p2041rdb: add NAND and NAND boot support powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards powerpc/85xx:Avoid vector table compilation for nand_spl powerpc/85xx:Fix IVORs addr after vector table relocation powerpc/85xx:Avoid hardcoded vector address for IVORs powerpc/p1023rds: Disable nor flash node and enable nand flash node
| * | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-04-30-261/+1047
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot cmd_bdinfo: display the address map size (32-bit vs. 36-bit) PowerPC: correct the SATA for p1/p2 rdb-pc platform powerpc/corenet_ds: Slave core in holdoff when boot from SRIO powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO powerpc/corenet_ds: Slave uploads ucode when boot from SRIO powerpc/corenet_ds: Slave module for boot from SRIO powerpc/corenet_ds: Master module for boot from SRIO powerpc/corenet_ds: Document for the boot from SRIO powerpc/corenet_ds: Correct the compilation errors about ENV powerpc/srio: Rewrite the struct ccsr_rio powerpc/85xx:Fix lds for nand boot debug info powerpc/p2041rdb: add env in NAND support powerpc/p2041rdb: add NAND and NAND boot support powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards powerpc/85xx:Avoid vector table compilation for nand_spl powerpc/85xx:Fix IVORs addr after vector table relocation powerpc/85xx:Avoid hardcoded vector address for IVORs powerpc/p1023rds: Disable nor flash node and enable nand flash node
| | * | | powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSRTimur Tabi2012-04-24-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur@freescale.com>
| | * | | powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-52/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | cmd_bdinfo: display the address map size (32-bit vs. 36-bit)Timur Tabi2012-04-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Freescale SOCs support 32-bit and 36-bit physical addressing, and U-Boot must be built to enable one or the other. Add this information to the bdinfo command. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | PowerPC: correct the SATA for p1/p2 rdb-pc platformJerry Huang2012-04-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For p1/p2 rdb-pc platform, use the PCIe-SATA Silicon Image SATA controller. Therefore, the SATA driver will use sata_sil, instead sata_sil3114. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com>
| | * | | powerpc/corenet_ds: Slave core in holdoff when boot from SRIOLiu Gang2012-04-24-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| | * | | powerpc/corenet_ds: Slave reads ENV from master when boot from SRIOLiu Gang2012-04-24-1/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| | * | | powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-5/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| | * | | powerpc/corenet_ds: Slave module for boot from SRIOLiu Gang2012-04-24-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| | * | | powerpc/corenet_ds: Master module for boot from SRIOLiu Gang2012-04-24-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| | * | | powerpc/corenet_ds: Document for the boot from SRIOLiu Gang2012-04-24-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| | * | | powerpc/corenet_ds: Correct the compilation errors about ENVLiu Gang2012-04-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| | * | | powerpc/srio: Rewrite the struct ccsr_rioLiu Gang2012-04-24-160/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| | * | | powerpc/85xx:Fix lds for nand boot debug infoPrabhakar Kushwaha2012-04-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently "u-boot", the elf file generated via u-boot-nand.lds does not contain required debug information i.e. .debug_{line, info, abbrev, aranges, ranges} into their respective _global_ sections. The original ld script line arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) is not entirely correct because the start.o file is already processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will not process start.o again for bootpg. So Fix u-boot-nand.lds to generate these debug information. Signed-off-by: Anmol Paralkar <b07584@freescale.com> Signed-off-by: John Russo <John.Russo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/p2041rdb: add env in NAND supportShaohui Xie2012-04-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add env in NAND support when boot from NAND. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/p2041rdb: add NAND and NAND boot supportShaohui Xie2012-04-24-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New P2041RDB board will add a NAND chip, so add support for NAND and NAND boot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boardsYork Sun2012-04-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-24-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-24-31/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/p1023rds: Disable nor flash node and enable nand flash nodeChunhe Lan2012-04-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the p1023rds, when system boots from nor flash, kernel only accesses nor flash and can not access nand flash with BR0/OR0; when system boots from nand flash, kernel only accesses nand flash and can not access nor flash with BR0/OR0. Default device tree nor and nand node should have the following structure: Example: nor_flash: nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x02000000>; bank-width = <2>; device-width = <1>; status = "okay"; partition@0 { label = "ramdisk"; reg = <0x00000000 0x01c00000>; }; } nand_flash: nand@1,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1023-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x00040000>; status = "disabled"; u-boot-nand@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; read-only; }; } When booting from nor flash, the status of nor node is enabled and the status of nand node is disabled in the default dts file, so do not do anything. But, when booting from nand flash, need to do some operations: o Disable the NOR node by setting status = "disabled"; o Enable the NAND node by setting status = "okay"; Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-04-30-7/+406
|\ \ \ \ \ | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: i2c:designware Turn off the ctrl when setting the speed i2c: Add support for designware i2c controller sh: i2c: Add support I2C controller of SH7734
| * | | | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-04-30-7/+406
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: i2c:designware Turn off the ctrl when setting the speed i2c: Add support for designware i2c controller sh: i2c: Add support I2C controller of SH7734
| | * | | | i2c:designware Turn off the ctrl when setting the speedArmando Visconti2012-04-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The designware i2c controller must be turned off before setting the speed in IC_CON register, as stated in the section 6.3.1 of the dw_apb_i2c_db.pdf. Signed-off-by: Michel Sanches <michel.sanches@st.com> Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
| | * | | | i2c: Add support for designware i2c controllerVipin KUMAR2012-04-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier, a driver exists in the u-boot source for designware i2c interface. That driver was specific to spear platforms. This patch implements the i2c controller as a generic driver which can be used by multiple platforms The driver files are now renamed to designware_i2c.c and designware_i2c.h and these are moved into drivers/i2c folder for reusability by other platforms Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
| | * | | | sh: i2c: Add support I2C controller of SH7734Nobuhiro Iwamatsu2012-04-24-0/+388
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas SH7734 has two I2C interfaceis. This supports these I2C. V5: - include i2c.h. - Add check of icsr bit polling logic. - Implement i2c_probe. V4: - Remove sh_i2c_dump_reg function. - Use puts() when there's no format. - Chnage check for I2C bus number. - Remove space before the semi-colon. V3: - Fix error for whitespace. V2: - Changed bit control to use the clr|set|clrsetbits_* functions. - Fix wrong comment style. - Add new line before for loop in i2c_read. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2024-11-09 19:26:56 +0000