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* fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal2011-09-29-0/+95
| | | | | | | | | | | | | | | | | | Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal2011-09-29-0/+17
| | | | | | | | | | | | | | | Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal2011-09-29-0/+10
| | | | | | | | | | | | | | | Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal2011-09-29-3/+4
| | | | | | | | | | | For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add NAND/NAND_SPL support to P1010RDBDipen Dudhat2011-09-29-0/+332
| | | | | | | | | And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-7/+1149
| | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: Add basic support for P1010RDBPoonam Aggrwal2011-09-29-0/+1477
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for new P102x/P2020 RDB style boardsLi Yang2011-09-29-0/+2289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
* powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2011-09-29-58/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi2011-09-29-277/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala2011-09-29-0/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh2011-09-29-3/+38
| | | | | | | | | | | | | Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Prepare v2011.09v2011.09Wolfgang Denk2011-09-29-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: versatile: delete split_by_variant.shLinus Walleij2011-09-28-42/+0
| | | | | | | | | Since commit d388298a59ba375c76597b8f95b560afa971a0fb by Stefano Babic this file is no longer needed so delete it. Cc: Stefano Babic <sbabic@denx.de> Cc: Loïc Minier <loic.minier@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Revert "phylib: remove a couple of redundant code lines"Wolfgang Denk2011-09-28-2/+5
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 041c542219af7f31c372d89b4c7c6f4c8064a8ce. The lines removed by this commit weren't redundant. The logic is (and probably should be better commented): Find the intersection of the advertised capabilities of both sides of the link (lpa). From that intersection, find the highest capability we can run at (that will be the negotiated link). Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL). The code will now set phydev->speed to 100, and phydev->duplex to 1, but this link does not support 100FULL. Kudos to Andy Fleming <afleming@gmail.com> for binging this to attention and for the explanation. Signed-off-by: Wolfgang Denk <wd@denx.de>
* doc/README.scrapyard: Update board removal commit IDsWolfgang Denk2011-09-28-13/+13
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-09-28-816/+2
|\ | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM: remove broken "ixdp425" and "ixpdg425" boards
| * ARM: remove broken "ixdp425" and "ixpdg425" boardsAlbert ARIBAUD2011-09-27-816/+2
| | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Stefan Roese <sr@denx.de>
* | ASIX: Fix buffer access in asix_get_phy_addr()Marek Vasut2011-09-24-1/+1
|/ | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-09-23-1/+1
|\ | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: OMAP3: beagle: Fix build warning in beagle.c
| * OMAP3: beagle: Fix build warning in beagle.cDirk Behme2011-09-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix build warning beagle.c:532: warning: initialization from incompatible pointer type Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Jason Kridner <jkridner@beagleboard.org> CC: Koen Kooi <koen@dominion.thruhere.net> CC: Joel A Fernandes <agnel.joel@gmail.com> Cc: Greg Turner <gregturner@ti.com> CC: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Jason Kridner <jkridner@beagleboard.org>
* | doc: provide a correct board_init_r definition pathVladimir Zapolskiy2011-09-23-1/+1
|/ | | | | | | | This is a trivial fix in the documentation, which corrects board_init_r() source reference. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Prepare v2011.09-rc2v2011.09-rc2Wolfgang Denk2011-09-22-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Minor Coding Style CleanupWolfgang Denk2011-09-22-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* km/common: fix bug in IVM mac address accessHolger Brunck2011-09-21-2/+2
| | | | | | | | The MAC address stored in the inventory eeprom begins at offset 1. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Wolfgang Denk <wd@denx.de>
* sf: fix debug format string warningVadim Bendebury2011-09-21-1/+1
| | | | | | | | On some systems, we get a warning when %lu is used with size_t's, so use the correct format string. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: turn name len check into an assertMike Frysinger2011-09-21-6/+1
| | | | | | | | | The new sanity check introduces a printf warning for some systems: eth.c:233: warning: format '%zu' expects type 'size_t', but argument 3 has type 'int' Rather than tweak the format string, use the new assert() helper instead. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ignore soc asm-offsets.sMike Frysinger2011-09-21-0/+1
| | | | | | | | Recent commit a4814a69d3bca6ee05f4bfc4 cleaned up generation of asm-offsets.s for SoC dirs, but missed adding it to the ignore list which makes it show up in `git status`. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Drop bogus BOOTFLAG_* definitionsWolfgang Denk2011-09-20-11/+0
| | | | | | | | | | There is no code anywhere that references BOOTFLAG_* so remove these defines. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Peter Tyser <ptyser@xes-inc.com>
* net/bootp.c: fix tftp load if autoload environment var isn't setPeter Korsgaard2011-09-19-1/+1
| | | | | | | | | | | | | Commit 093498669 (Put common autoload code into auto_load() function) broke handling of autoload environment variable not being set. The bootp/dhcp code will just keep on requesting IP address forever and never start TFTP download. Fix it by moving TftpStart() outside the conditional like it was before. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* ppc4xx: Flush dcache after DDR2 autocalibration with caches onStefan Roese2011-09-19-0/+7
| | | | | | | | Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
* Fix incorrect array size of phy settings for 405EXWeirich, Bernhard2011-09-19-1/+1
| | | | | | | | Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since 405EX has 2 ethernet interfaces. Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net> Signed-off-by: Stefan Roese <sr@denx.de>
* DA830: Fix Build WarningSandeep Paulraj2011-09-13-1/+2
| | | | | | This commit fixes a build warning in the DA830 EVM build Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* led: remove camel casing of led identifiers globallyJason Kridner2011-09-13-113/+113
| | | | | | | | | | | | | | | Result of running the following command to address Wolfgang's comment about camel case: for file in `find . | grep '\.[chS]$'`; do perl -i -pe 's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done Discussion: http://patchwork.ozlabs.org/patch/84988/ Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: fix pad configuration settings for SDP and PandaAneesh V2011-09-13-28/+22
| | | | | | | | | omap4: fix pad configuration settings for SDP and Panda Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sebastien Jan <s-jan@ti.com> Signed-off-by: David Anders <x0132446@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: IO settingsAneesh V2011-09-13-45/+105
| | | | | | | | Tuning some IO settings for better performance and power. And consolidate all such IO settings at one place. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: make SDRAM init work for ES1.0 siliconAneesh V2011-09-13-54/+22
| | | | | | | | | | | | SDRAM init was not working on ES1.0 due to a programming error. A pointer that was passed by value to a function was set in function emif_get_device_details(), but the effect wouldn't be seen in the calling function. The issue came out while testing for ES1.0 because ES1.0 doesn't have any SDRAM chips connected to CS1 Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: factor out common part from board config headersAneesh V2011-09-13-476/+288
| | | | | | | | Factor out common parts from omap4_sdp4430.h and omap4_panda.h into a new file omap4_common.h Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: gpio: Adapt board files to use generic APISanjeev Premi2011-09-13-112/+112
| | | | | | | This patch contains updates the sources in the board files to use the generic API. Signed-off-by: Sanjeev Premi <premi@ti.com>
* omap: gpio: generic changes after changing APISanjeev Premi2011-09-13-12/+13
| | | | | | | | This patch contains the generic changes required after change to generic API in the previous patch. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: gpio: Use generic APISanjeev Premi2011-09-13-46/+82
| | | | | | | | | | | | | | | Convert all OMAP specific functions to use the common API definitions in include/asm/gpio.h. In the process, made few additional changes: - Use -EINVAL consistently. -1 was used in many places. - Removed one-liner static functions that were used only once. Replaced the content as necessary. - Combines implementation of functions omap_get_gpio_dataout() and omap_get_gpio_datain(). To do so, new static function _get_gpio_direction() was added. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3 Beagle: Minor config cleanupSandeep Paulraj2011-09-12-1/+0
| | | | | | This patch removes a hardcoded MAC address Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* da830: modify the MEMTEST start and end addressNagabhushana Netagunte2011-09-12-4/+4
| | | | | | | | | | Modify the MEMTEST start and end address. The memtest range was overlapping the CONFIG_SYS_LOAD_ADDR which causes the uImage to be corrupt.Also, modify the size for which mtest is run to 32MB from 16MB. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* da830: enable SPI flash boot modeNagabhushana Netagunte2011-09-12-3/+4
| | | | | | | | | | | Enable SPI flash boot mode in configuration file as default. With the introduction of 456MHz part, SPI operating frequency will increase and at this frequency SPI does not work correctly. Hence reduce the default SPI speed to 30MHz from 50MHz. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* da830: modify the U-Boot prompt stringNagabhushana Netagunte2011-09-12-1/+1
| | | | | | | | | | Modify U-boot promt string from 'DA830-evm >' to 'U-Boot >' as there are many variants of da830 based boards which have diffrent names such as L137, AM1707 etc. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ARMV7: OMAP3: Add 37xx ESx revision numbers.Howard D. Gray2011-09-12-1/+22
| | | | | | | | OMAP3: Add 37xx ESx revision numbers. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Signed-off-by: Howard D. Gray <howard.gray@matrix-vision.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ARMV7: OMAP: I2C driver: cosmetic: make checkpatch-compatibleMichael Jones2011-09-12-52/+53
| | | | | | Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ARMV7: OMAP: Write more than 1 byte at a time in i2c_writeMichael Jones2011-09-12-78/+58
| | | | | | | | | | This allows the EEPROM layer to send a single i2c write command per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between i2c write commands. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP: Add function to get state of a GPIO outputJoel A Fernandes2011-09-12-0/+22
| | | | | | | | Read directly from OMAP_GPIO_DATAOUT to get the output state of the GPIO pin Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* MX25: tx25: Cleanup tx25.h configFabio Estevam2011-09-12-8/+6
| | | | | | Cleanup tx25.h by removing unnecessary defines and by removing unneeded "1"'s. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-11-02 09:25:45 +0000