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* x86: Add support for MTRRsSimon Glass2015-01-13-101/+187
| | | | | | | | | | | | | | Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
| | | | | | | | | | This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Display vesa modes in hexSimon Glass2015-01-13-2/+2
| | | | | | | | The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up VESA mode numbersSimon Glass2015-01-13-4/+7
| | | | | | | There are some bits which should be ignored when displaying the mode number. Make sure that they are not included in the mode that is displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use cache, don't clear the display in video BIOSSimon Glass2015-01-13-3/+2
| | | | | | | There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-13-1/+8
| | | | | | | | | | | | This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case. We could add a command to run the video BIOS later when needed, but this is not considered at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Add debug option to time the BIOS copySimon Glass2015-01-13-0/+3
| | | | | | | | This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Don't return a vesa mode when there is not videoSimon Glass2015-01-13-1/+1
| | | | | | | If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: video: Add a debug() to display the frame buffer addressSimon Glass2015-01-13-0/+1
| | | | | | Provide a way to display this address when booting. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Correct ifdtool microcode calculationSimon Glass2015-01-13-2/+2
| | | | | | | | This currently assumes that U-Boot resides at the start of ROM. Update it to remove this assumption. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop RAMTOP KconfigSimon Glass2015-01-13-12/+0
| | | | | | | We don't need this in U-Boot since we calculate it based on available memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct XIP_ROM_SIZESimon Glass2015-01-13-1/+1
| | | | | | | This should default to the size of the ROM for faster execution before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add pci devices in the dts fileBin Meng2015-01-13-0/+81
| | | | | | | | | | | | | The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings. Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use ePAPR defined properties for x86-uartBin Meng2015-01-13-4/+9
| | | | | | | | | Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* serial: ns16550: Support ns16550 compatible pci uart devicesBin Meng2015-01-13-0/+31
| | | | | | | | | | | | | | There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* fdt: Add several apis to decode pci device nodeBin Meng2015-01-13-26/+257
| | | | | | | | | | | | | | This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
* x86: Simplify the fsp hob access functionsBin Meng2015-01-12-100/+101
| | | | | | | | | Remove the troublesome union hob_pointers so that some annoying casts are no longer needed in those hob access routines. This also improves the readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Make pci apis usable before relocationBin Meng2015-01-12-14/+28
| | | | | | | | | | | | | | Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support pci bus scan in the early phaseBin Meng2015-01-12-0/+1
| | | | | | | | | On x86, some peripherals on pci buses need to be accessed in the early phase (eg: pci uart) with a valid pci memory/io address, thus scan the pci bus and do the corresponding resource allocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng2015-01-12-0/+2
| | | | | | | | arch/x86/cpu/pci.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up the board dts filesBin Meng2015-01-12-24/+7
| | | | | | | | | | | | | | | | This commits cleans up the board dts files. - Correct the serial port register size to 8 - Remove the misleading status = "disabled" statement in the serial.dtsi - Move the inclusion of skeleton.dtsi from serial.dtsi to board dts files - Let the board dts file define stdout-path in the chosen node - Remove device nodes in board dts files thar are duplicated to skeleton.dtsi Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Rename coreboot.dsti to serial.dtsiBin Meng2015-01-12-2/+2
| | | | | | | | The name of coreboot.dtsi is misleading, as it actually describes the legacy serial port device node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove alex.dts in arch/x86/dtsBin Meng2015-01-12-25/+0
| | | | | | | No board is using alex.dts, so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Prepare v2015.01Tom Rini2015-01-12-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Nokia RX-51: Do not call secure PPA routine on non secure devicesPali Rohár2015-01-12-1/+5
| | | | | | | | | | | | | Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only on real secure device and not in qemu. This board patch just disable calling secure PPA routine on non secure devices. Qemu implements GP device and with this patch u-boot is working in qemu again. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz>
* powerpc: xes: Add maintainerPeter Tyser2015-01-12-4/+4
| | | | | | Add Peter Tyser as the maintainer of Extreme Engineering Solutions products. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* powerpc: xes: Convert to generic boardJohn Schmoller2015-01-12-0/+10
| | | | | | | | Convert Extreme Engineering Solutions products to use generic board support. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ARM: remove redudant information from Kconfig filesMasahiro Yamada2015-01-12-30/+0
| | | | | | | | | - "string" type for SYS_* is defined in arch/Kconfig - SYS_CPU "armv7" has been replaced with "select CPU_V7" - SYS_SOC "tegra124" is already defined in tegra124/Kconfig Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* omap: beagle_x15: add MAINTAINERSMasahiro Yamada2015-01-12-0/+6
| | | | | | | | Commit 1e4ad74b875f (beagle_x15: add board support for Beagle x15) missed to add board/ti/beagle_x15/MAINTAINERS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Felipe Balbi <balbi@ti.com>
* stv0991: record defconfig ownership in MAINTAINERSMasahiro Yamada2015-01-12-0/+1
| | | | | | | | This commit fixes warnings reported by tools/genboardscfg.py. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Vikas Manocha <vikas.manocha@st.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: kirkwood: dns325: Add generic board supportStefan Herbrechtsmeier2015-01-12-0/+1
| | | | Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
* Change e-mail address of Stefan HerbrechtsmeierStefan Herbrechtsmeier2015-01-12-6/+6
| | | | Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
* common/board_f.c: fix compile error when tracing disabledKevin Hilman2015-01-12-7/+0
| | | | | | | | | | | | | | | | When CONFIG_TRACE is disabled, linking fails with: common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to `trace_early_init' To fix, wrap trace init calls with #ifdef CONFIG_TRACE. While at it, remove the static inline version of the init call from trace.h as suggested by Simon Glass, since it doesnt work. Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* tools/kwbimage.c: fix parser error handlingAndreas Bießmann2015-01-11-6/+8
| | | | | | | | | | | | | | | | | | | | The two error checks for image_boot_mode_id and image_nand_ecc_mode_id where wrong and would never fail, fix that! This was detected by Apple's clang compiler: ---8<--- HOSTCC tools/kwbimage.o tools/kwbimage.c:553:20: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare] if (el->bootfrom < 0) { ~~~~~~~~~~~~ ^ ~ tools/kwbimage.c:571:23: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare] if (el->nandeccmode < 0) { ~~~~~~~~~~~~~~~ ^ ~ 2 warnings generated. --->8--- Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-By: Jeroen Hofstee <jeroen@myspectrum.nl>
* ARM: atmel: sama5d3xek: fix the LCD parametersBo Shen2015-01-11-2/+1
| | | | | | Remove unused vsync parameter, and correct the include file. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: sama5d4xek: fix the LCD parametersBo Shen2015-01-11-2/+1
| | | | | | Remove unused vsync parameter, and correct the include file. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: sama5d4 xplained: fix the LCD parametersBo Shen2015-01-11-4/+2
| | | | | | | Correct the LCD pixel clock, remove unused vsync parameter, and also correct the include file. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* fix: tools: kwbimage.c: Initialize headersz to suppress warningŁukasz Majewski2015-01-10-1/+1
| | | | | | | | | | | | | | | | When building with my toolchain (4.8.2): CROSS_COMPILE=/home/lukma/work/ptxdist/toolchains/arm/OSELAS.Toolchain-2013.12.0/arm-v7a-linux-gnueabi/gcc-4.8.2-glibc-2.18-binutils-2.24-kernel-3.12-sanitized/bin/arm-v7a-linux-gnueabi- I see following WARNING: tools/kwbimage.c: In function "kwbimage_set_header": tools/kwbimage.c:803:8: warning: "headersz" may be used uninitialized in this function [-Wmaybe-uninitialized] memcpy(ptr, image, headersz); ^ This fix aims to suppress it. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-01-10-10/+5
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| * mtd: nand: do not scan BBT after scrubMasahiro Yamada2015-01-09-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, "nand scrub" runs chip->scan_bbt at the end of nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set. It violates the intention of NAND_SKIP_BBTSCAN. Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set. Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt() right after scrub. We can be lazier here because the BBT is scanned at the next call of nand_block_checkbad(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
| * mtd: nand: Mark the BBT as scanned prior to calling scan_bbt againMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning) broke NAND_BBT_USE_FLASH feature. Its git-log claimed that it reinstated the change as by commit fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved "chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);". It causes recursion if scan_bbt does not find a flash based BBT and tries to write one, and the attempt to erase the BBT area causes a bad block check. Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to calling scan_bbt.). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rostislav Lisovy <lisovy@merica.cz> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com>
| * mtd: nand: revive "nand scrub" commandMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | | | | | | | | | | Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14), the "nand scrub" command has not been working. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* | arc: introduce "mdbtrick" targetAlexey Brodkin2015-01-09-0/+15
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MetaWare debugger (MDB) is still used as a primary tool for interaction with target via JTAG. Moreover some very advanced features are not yet implemented in GDB for ARC (and not sure if they will be implemnted sometime soon given complexity and rare need for those features for common user). So if we're talking about development process when U-Boot is loaded in target memory not by low-level boot-loader but manually through JTAG chances are high developer uses MDB for it. But MDB doesn't support PIE (position-independent executable) - it will refuse to even start - that means no chance to load elf contents on target. Then the only way to load U-Boot in MDB is to fake it by: 1. Reset PIE flag in ELF header This is simpe - on attempt to open elf MDB checks header and if it doesn't match its expectation refuces to use provided elf. 2. Strip all debug information from elf If (1) is done then MDB will open elf but on parsing of elf's debug info it will refuse to process due to debug info it cannot understand (symbols with PIE relocation). Even though it could be done manually (I got it documented quite a while ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated way is very convenient. User may build U-Boot that will be loaded on target via MDB saying "make mdbtrick". Then if we now apply the manipulation MDB will happily start and will load all required sections into the target. Indeed there will be no source-level debug info available. But still MDB will do its work on showing disassembly, global symbols, registers, accessing low-level debug facilities etc. As a summary - this is a pretty dirty hack but it simplifies life a lot for us ARc developers. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de>
* arm: vf610: fix boot from SD-cardStefan Agner2015-01-09-1/+4
| | | | | | | | | | | | | | | | Boot from SD-card (and probably also from NAND) was broken since commit d6d07a9bec ("arm: vf610: add NAND support for vf610twr"). It looks like the increased size of U-Boot lead to a situation where the boot ROM overwrote its own stack/heap while loading U-Boot from the SD-card to the SRAM. However, U-Boot worked fine when loaded through USB serial loader directly into SRAM. It looks like loading from SD-card uses other stack/heap location then the serial loader (or maybe no stack or heap at all). This fix moves U-Boot to gfxRAM, which is 512kB in size and is not used by the boot ROM nor the SD-card loader of it. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* arm: build arch memset/memcpy in Thumb2 modeStefan Agner2015-01-09-87/+142
| | | | | | | | | | | | | | | | | | | | | | Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-58/+316
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| * imx:mx6sxsabresd support qspi AHB readPeng Fan2015-01-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_SYS_FSL_QSPI_AHB in header file to enable AHB in driver. In order to count the time, add CONFIG_CMD_TIME. Using AHB read can improve the the read speed about 30%. AHB read: => time sf read 0x8f800000 0 100000 SF: 1048576 bytes @ 0x0 Read: OK time: 0.174 seconds => time sf read 0x8f800000 1000000 100000 SF: 1048576 bytes @ 0x1000000 Read: OK time: 0.174 seconds IP read: => time sf read 0x8f800000 0 100000 SF: 1048576 bytes @ 0x0 Read: OK time: 0.227 seconds => time sf read 0x8f800000 1000000 100000 SF: 1048576 bytes @ 0x1000000 Read: OK time: 0.227 seconds Note: Quad read is not supported in driver, now. In my side, using AHB and Quad read can achieve about 16MB/s. Anyway, I have plan to reimplement the driver using DTB and DM, then make the code cleaner and more feature can be added. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * qspi:fsl implement AHB readPeng Fan2015-01-09-10/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]Axel Lin2015-01-08-24/+12
| | | | | | | | | | | | | | No functional change, just simplify the code a bit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: cadence_qspi: Fix checking return value of fdt_first_subnode()Axel Lin2015-01-07-1/+1
| | | | | | | | | | | | | | | | fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found. 0 is supposed to be a valid offset returns from fdt_first_subnode(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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