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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-01-04-0/+0
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| * ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-453/+224
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| * | imx:mx6slevk add spi nor boot supportPeng Fan2014-12-31-1/+16
| | | | | | | | | | | | | | | | | | | | | Add spi nor boot support for mx6slevk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | imx:mx6sxsabresd add qspi supportPeng Fan2014-12-31-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the pad setting and enable qspi clock to support qspi flashes access. Add QSPI related macro in configuration header file. Note: mx6sxsabresd Revb board, 32M flash is used, but in header file, CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT initialization qspi_set_lut function uses 32BIT addr, however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to access bigger than 16MB size flash, and BRRD/BRWR should also be supported. Future patches will fix this. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | imx:qspi add 4K erase supportPeng Fan2014-12-31-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add 4k erase command support for qspi driver. reuse the 64k erase function, but change the function name from qspi_op_se to qspi_op_erase, since it supports 64k and 4k erase. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | arm:mx6sx add QSPI supportPeng Fan2014-12-31-6/+76
| | | | | | | | | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | QuadSPI: use correct amba_basePeng Fan2014-12-31-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | According cs, use different amba_base to choose the corresponding flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will choose the same flash device, but not different flash devices. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | QuadSPI: use QSPI_CMD_xx instead of flash opcodesPeng Fan2014-12-31-31/+33
| | | | | | | | | | | | | | | | | | | | | Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | sf: sf_params: Add S25FL164K flash identifier infoAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | sf: sf_params: Add S25FL116K flash supportAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | Added S25FL116K flash and tested on Marvell 88F6281 based system. Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | mtd/spi: Add support for SST25WF040BShengzhou Liu2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add support for SST25WF040B-40I-SN flash. Tested on T1024QDS board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | mtd: sf: Zap ramtron driverJagannadha Sutradharudu Teki2014-12-18-405/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Removed ramtron driver since the EMK boards are no longer been active, and these are the only boards used this flash driver. Commit details for EMK zap: "ppc/arm: zap EMK boards" (sha1: d58a9451e7339ed4cf2b2627e534611f427fb791) Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-44/+4433
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| * | net: rtl8169: Add support for RTL-8168/8111gThierry Reding2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This network interface card is found on the NVIDIA Jetson TK1. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Use non-cached memory if availableThierry Reding2014-12-18-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To work around potential issues with explicit cache maintenance of the RX and TX descriptor rings, allocate them from a pool of uncached memory if the architecture supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Properly align buffersThierry Reding2014-12-18-29/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX and TX descriptor rings should be aligned to 256 byte boundaries. Use the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't have to be manually aligned later on. Also make sure that the buffers do align to cache-line boundaries in case the cache-line is higher than the 256 byte alignment requirements of the NIC. Also add a warning if the cache-line size is larger than the descriptor size, because the driver may discard changes to descriptors made by the hardware when requeuing RX buffers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFERThierry Reding2014-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the top-level README file, this configuration setting can be used to override the number of receive buffers that an ethernet NIC uses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable non-cached memoryThierry Reding2014-12-18-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards, most notably those with a PCIe ethernet NIC, require this to avoid cache coherency problems. Since the option adds very little code and overhead enable it across all Tegra generations. Other drivers may also start supporting this functionality at some point, so enabling it now will automatically reap the benefits later on. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding2014-12-18-0/+412
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra124 PCIe device tree nodeThierry Reding2014-12-18-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra124Thierry Reding2014-12-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on BeaverThierry Reding2014-12-18-0/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. In addition the board has a mini-PCIe expansion slot. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on CardhuThierry Reding2014-12-18-0/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding2014-12-18-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra30Thierry Reding2014-12-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on TrimSliceThierry Reding2014-12-18-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding2014-12-18-1/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+1150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable XUSB pad controller on Jetson TK1Thierry Reding2014-12-18-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add XUSB pad controller on Tegra124Thierry Reding2014-12-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+794
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement powergate supportThierry Reding2014-12-18-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Provide PCIEXCLK reset IDThierry Reding2014-12-18-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement tegra_plle_enable()Thierry Reding2014-12-18-0/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | power: Add AMS AS3722 PMIC supportThierry Reding2014-12-18-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: colibri_t30: comment style fixMarcel Ziswiler2014-12-18-4/+8
| |/ | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-31-0/+719
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: include/configs/arndale.h Signed-off-by: Tom Rini <trini@ti.com>
| * | usb: eth: enable AX88179 DRIVER for ARNDALE 5250Rene Griessl2014-12-31-0/+1
| | | | | | | | | | | | | | | | | | Patch enables AX88179 driver for ARNDALE 5250 Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
| * | usb: eth: add ASIX AX88179 DRIVERRene Griessl2014-12-31-0/+714
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network adapter. Driver has been tested on the RECS5250 COM module (similar to ARDALE5250). Testcase was DHCP and PXE boot. Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-30-2/+12
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| * | | arm: socfpga: Change watchdog timeoutStefan Roese2014-12-21-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-30-292/+742
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| * | | | mx6slevk: Remove get_board_rev()Fabio Estevam2014-12-30-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_board_rev() just returns the cpu revision, which does not make it really useful for distinguishing between revisions of the board. Let's get rid of get_board_rev() as it is not being used with its correct meaning. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | arm: mx6: novena: Add proper LVDS display supportMarek Vasut2014-12-30-23/+401
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Repair the register configuration and add proper support for the display attached to both LVDS channels. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | | arm: mx6: novena: Pull video handling into separate fileMarek Vasut2014-12-30-78/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull all of the video handling into a separate file, since a lot more code will be added and such code would polute the board file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | | arm: mx6: novena: Pull GPIO definitions into headerMarek Vasut2014-12-30-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull the definitions of GPIOs into a separate header file, so that they can be used across all source files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | | arm: mx6: novena: Minor config file fixMarek Vasut2014-12-30-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sequence like the following is completely useless and results from an errorneous ordering of the statements during development. Zap it. #ifdef FOO #define FOO Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | | arm: mx6: novena: Minor coding style fixMarek Vasut2014-12-30-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just zap multiple spaces and replace them with tabs properly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
generated by cgit v1.1 at 2024-11-09 15:27:28 +0000