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* Merge branch 'master' of git://git.denx.de/u-boot-onenandTom Rini2014-01-06-1/+7
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| * mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* | PowerPC: Drop linkstation_HGLAN supportTom Rini2013-12-20-1135/+0
|/ | | | | | | | | With changes to the rtl8169 ethernet to improve cache support, we have needed additional cache functions for mpc8245. As the board maintainer has been unresponsive, remove this board. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
* ARM: Samsung: Change GONI and Universal_C210 maintainers.Łukasz Majewski2013-12-20-2/+2
| | | | | | | | Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers entry. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-14/+333
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| * driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * config: dra7_evm: Add Bank Address Register(BAR) configPoddar, Sourav2013-12-19-0/+1
| | | | | | | | | | | | | | | | Add config to support bank address register. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: tegra: clear RDY bit prior to every transferYen Lin2013-12-19-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+316
| | | | | | | | | | | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: add support for MX25L2006ELuka Perkov2013-12-18-0/+1
| | | | | | | | | | | | | | Add support for Macronix MX25L2006E SPI flash. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: probe: Hex values are in lower caseLuka Perkov2013-12-18-1/+1
| | | | | | | | | | | | | | | | All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-12-18-48/+62
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| * | mtd: nand: omap: fix ecc ops assignment when changing eccNikita Kiryanov2013-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | mtd: nand: omap: fix sw->hw->sw ecc switchNikita Kiryanov2013-12-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values into the current nand chip's ecc.layout struct. This is done under the assumption that the struct exists only to store values, so it is OK to overwrite it, but there is at least one situation where this assumption is incorrect: When switching to 1 bit hamming code sw ecc, the job of assigning layout data is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a pointer to an existing struct prefilled with the appropriate values. This struct doubles as both data and layout definition, and therefore shouldn't be overwritten, but on the next switch to hardware ecc, this is exactly what's going to happen. The next time the user switches to software ecc, they're going to get a messed up ecc layout. Prevent this and possible similar bugs by explicitly using the private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | nand_util.c: Use '%zd' for length in nand_unlock debug printTom Rini2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | length is size_t so needs to be '%zd' not '%d' to avoid warnings. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.sizeNikita Kiryanov2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way software ECC is configured, both during boot, and during ecc switch, in a way that is not backwards compatible with older systems: Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring for software ecc, relying on nand_scan_tail() to select a default for ecc.size (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize, which is likely to not be 256. Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert to the original behavior. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Pekon Gupta <pekon@ti.com>
| * | mtd: nand: omap_gpmc: cosmetic: Fix indentationStefan Roese2013-12-17-43/+45
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: wrap some long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: nand: omap: fix ecc-layout for HAM1 ecc-schemepekon gupta2013-12-17-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-12-18-9/+79
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| * | | usb: ehci: Fix register accessMarek Vasut2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the register access in EHCI HCD. We need to use address of the register as an ehci_writel() argument. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | usb: ehci: Do not de-init uninited controllersMarek Vasut2013-12-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the controller is not initialized, we shall not de-initialize it. As the control structure will not be filled, we will produce a null ptr dereference if the controller is not inited. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | usb: ehci-pci: Clarify and cleanup the EHCI controller detectionMarek Vasut2013-12-18-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The detection function of the EHCI PCI controller was really cryptic, add a beefy comment and clean the portion of the code up a bit. No change in the logic of the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | ARM: trats: dfu: Enable default Poll Timeout for Trats boardLukasz Majewski2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Provide default Poll Timeout value for Trats board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | usb: f_dfu: cosmetic: Code cleanupLukasz Majewski2013-12-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Code cleanup for dfu_bind_config function Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout valueLukasz Majewski2013-12-18-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to deter the host from sending subsequent DFU_GETSTATUS request in the case of e.g. writing the buffer to medium. Here the timeout is increased when we fill up the whole buffer. This delay allows eMMC memory to perform its internal operations. Otherwise we end up with HOST's error regarding GET_STATUS receive timeout. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | dfu: Export allocated dfu buffer sizeLukasz Majewski2013-12-18-0/+6
| | |/ | |/| | | | | | | | | | | | | | | | The method for exporting size of allocated buffer is provided. It is afterwards used by USB's dfu function code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | Makefile: fix broken pipe error for lcd4_lwmon5 boardMasahiro Yamada2013-12-18-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, a broken pipe error sometimes happened when building lcd4_lwmon5 board with Buildman. This commit re-writes build rules of u-boot.spr and u-boot-img-spl-at-end.bin more simply without using a pipe. Besides fixing a broken pipe error, this commit gives us other advantages: - Do not generate intermidiate files, spl/u-boot-spl.img and spl/u-boot-spl-pad.img for creating u-boot.spr - Do not generate an intermidiate file, u-boot-pad.img for creating u-boot-img-spl-at-end.bin Such intermidiate files were not deleted by "make clean" or "make mrpropr". Nor u-boot-pad.img was ignored by git. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Makefile: fix the typo error for mrproperBo Shen2013-12-18-1/+1
|/ / | | | | | | | | | | | | Fix the typo error for mrproper from mkproper. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Simon Glass <sjg@chromium.org>
* | serial_sh: add support for SH7753Yoshihiro Shimoda2013-12-18-1/+3
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | net: sh-eth: add support for SH7753Yoshihiro Shimoda2013-12-18-2/+6
| | | | | | | | | | | | | | | | SH7753 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sh: add support for sh7753evb boardYoshihiro Shimoda2013-12-18-0/+1368
|/ | | | | | | | | | | The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Prepare v2014.01-rc2Tom Rini2013-12-16-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-12-16-1/+1
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| * video: ipu_disp: Return a negative value on errorFabio Estevam2013-12-04-1/+1
| | | | | | | | | | | | We should return a negative error number (-EINVAL) on error. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-16-18/+36
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| * | blackfin: remove build warningSonic Zhang2013-12-16-10/+15
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: fixing warning by including proper headersSonic Zhang2013-12-16-1/+6
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: fix building error by enlarging the memory sizeSonic Zhang2013-12-16-5/+7
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: Disable commands to reduce l1 ram requirementSonic Zhang2013-12-16-2/+6
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: fix building error by adding macro CONFIG_SYS_I2CSonic Zhang2013-12-16-0/+1
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: fix build error by adding CONFIG_BFIN_SERIALSonic Zhang2013-12-16-0/+1
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | Makefile, .gitignore: Cleanup non-existing binariesMasahiro Yamada2013-12-16-9/+2
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | examples: x86: delete 82559_eepromMasahiro Yamada2013-12-16-364/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fea25720 renamed arch/i386 to arch/x86. But it missed to modify examples/standalone/Makefile. Since then, examples/standalone/82559_eeprom has never compiled and nobody has noticed that. After some discussion on ML, we agreed to delete this example. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)Masahiro Yamada2013-12-16-43/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert like follows: CPU mpc83xx -> CONFIG_MPC83xx CPU mpc85xx -> CONFIG_MPC85xx CPU mpc86xx -> CONFIG_MPC86xx CPU mpc5xxx -> CONFIG_MPC5xxx CPU mpc8xx -> CONFIG_8xx CPU mpc8260 -> CONFIG_8260 CPU ppc4xx -> CONFIG_4xx CPU x86 -> CONFIG_X86 ARCH x86 -> CONFIG_X86 ARCH powerpc -> CONFIG_PPC Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Makefile: delete unnecessary linesMasahiro Yamada2013-12-16-5/+0
| | | | | | | | | | | | | | | | | | REMOTE_BUILD is not used any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | README.vxworks: add a document describing the new VxWorks boot interfaceMiao Yan2013-12-16-0/+19
| | | | | | | | | | | | Signed-off-by: Miao Yan <miao.yan@windriver.com>
* | | common/fdt_support.c: avoid unintended return from fdt_fixup_memory_banks()Miao Yan2013-12-16-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdt_fixup_memory_banks() will add and update /memory node in device tree blob. In the case that /memory node doesn't exist, after adding a new one, this function returns error. The correct behavior should be continuing to update its properties. Signed-off-by: Miao Yan <miao.yan@windriver.com>
* | | common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot ↵Miao Yan2013-12-16-12/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interface. The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware description mechanism. For PowerPC, the boot interface conforms to the ePAPR standard, which is: void (*kernel_entry)(ulong fdt_addr, ulong r4 /* 0 */, ulong r5 /* 0 */, ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */, ulong r8 /* 0 */, ulong r9 /* 0 */) For ARM, the boot interface is: void (*kernel_entry)(void *fdt_addr) Signed-off-by: Miao Yan <miao.yan@windriver.com> [trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC, missing extern ft_fixup_num_cores] Signed-off-by: Tom Rini <trini@ti.com>
* | | common/config_defaults.h: make CONFIG_BOOTM_VXWORKS default configurationMiao Yan2013-12-13-0/+1
| | | | | | | | | | | | Signed-off-by: Miao Yan <miao.yan@windriver.com>
* | | common/cmd_bootm.c: seperate do_bootm_vxworks related code from CONFIG_CMD_ELF.Miao Yan2013-12-13-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_bootm_vxworks now is available under the configuration option CONFIG_BOOTM_VXWORKS, thus aligned with other operating systems that supported by bootm command. The bootvx command still depneds on CONFIG_CMD_ELF. Signed-off-by: Miao Yan <miao.yan@windriver.com>
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