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* ARM: arm1176: enable instruction cache in arch_cpu_init()Stephen Warren2012-09-01-0/+7
| | | | | | | | | Note that this affects all users of the ARM1176 CPU that enable CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as tnetv107x. Cc: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* README: fix references to config_cmd_default.hStephen Warren2012-09-01-2/+2
| | | | | | | All usage of config_cmd_default.h uses <> for the include statement. Update the README to do the same, rather than using "". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* snowball: Adding board specific cache cleanup routineMathieu J. Poirier2012-09-01-0/+26
| | | | | | | | Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* armv7: Adding cpu specific cache managmenentMathieu J. Poirier2012-09-01-0/+8
| | | | | | | | Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Separating mmc config parameters from driverJohn Rigby2012-09-01-88/+213
| | | | | | | | | | Configuration in vexpress and u8500.v1 is different from what is needed in u8500.v2. As such, card configuration specifics need to reside in the board file rather than the driver. Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* u8500: Enabling power to MMC device on AB8500 V2Mathieu J. Poirier2012-09-01-28/+94
| | | | | | | | | Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* u8500: Moving processor-specific functions to cpu area.Mathieu J. Poirier2012-09-01-74/+82
| | | | | | | | | | Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* snowball: applying power to LAN and GBF controllersMathieu J. Poirier2012-09-01-3/+103
| | | | | | | | LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Moving to ux500.v2 addess scheme for PRCMU accessMathieu J. Poirier2012-09-01-32/+71
| | | | | | | | Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding CPU clock initialisationMathieu J. Poirier2012-09-01-4/+37
| | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding architecture dependent initialisationMathieu J. Poirier2012-09-01-8/+93
| | | | | | | Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Moving prcmu to cpu directoryMathieu J. Poirier2012-09-01-9/+8
| | | | | | | | This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Add support for ux500 based snowball boardMathieu J. Poirier2012-09-01-0/+1657
| | | | | | | | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Acked-by: Tom Rini <trini@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/gpio/Makefile
* davinci, c6x: Always use C version of reset codeTom Rini2012-09-01-84/+34
| | | | | | | | | We can safely use the same reset code written in C for both Davinci and C6X platforms. In addition the C version of the code is marginally smaller on Davinci. Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* arm: omap: Fix switching back to nandecc sw.Jeroen Hofstee2012-09-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | Orjan Friberg wrote at [1]: "For the beagleboard, ecc.size is not explicitly set when doing 'nandecc sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's set to 256 bytes. When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly the format has changed." No patch has been submitted and the issue was still present. This patch adds the mentioned solution. Tested on a tam3517 board. [1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html cc: Orjan Friberg <of@flatfrog.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
* davinci: enbw_cmc: change switch init behaviourHeiko Schocher2012-09-01-33/+69
| | | | | | | | | | | | | | | | | | | change the behaviour of switch initialization: - rename "pwl" to "lan" in hwconfig parameter "lan" = port 1 with phy addr 2 "lmn" = port 2 with phy addr 3 - if we have a valid switch config file in flash, do not evaluate the settings in the hwconfig "lan" or "lmn" subcommand. - if we have no valid switch config file in flash, start the switch with default values, if we have a "lan" or a "lmn" hwconfig subcommand. If no "lan" or "lmn" is found in hwconfig, do nothing with the switch. Signed-off-by: Heiko Schocher <hs@denx.de>
* am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya2012-09-01-1/+7
| | | | | | | | | | | | | | | This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
* da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu2012-09-01-4/+116
| | | | | | | | | | Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stackTom Rini2012-09-01-0/+1
| | | | | | | | Make sure that when we setup the stack before calling s_init() we have the stack have 8-byte alignment for ABI compliance. Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
* omap4/5/am33xx: Make lowlevel_init available to all armv7 platformsTom Rini2012-09-01-36/+63
| | | | | | | | | | | | | | Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
* am335x evm: Enable support for spi0Tom Rini2012-09-01-0/+30
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support, update omap3 McSPI driverTom Rini2012-09-01-0/+16
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am335x evm: Enable MMC1 pinmuxTom Rini2012-09-01-0/+16
| | | | | | | MMC1 is available in profile 2 on the GP EVM and is exposed on the expansion header on beaglebone. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct MMC1, remove MMC2 supportTom Rini2012-09-01-4/+9
| | | | | | | | - Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
* am335x evm: Initial support for AM335x GP EVM ProfilesTom Rini2012-09-01-4/+42
| | | | | | | | | The AM335x GP EVM can have one of 8 different profiles selected. Each profile has a different set of peripherals and requires different pinmux configurations that conflict with other profiles. i2c1 is an example of a conflicted mux currently. Signed-off-by: Tom Rini <trini@ti.com>
* sc_sps_1: Adjust board config to use 'mxs' SoC codeOtavio Salvador2012-09-01-7/+7
| | | | | | | Fix build failure due the move of mx28 code to 'mxs' SoC. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* rtc: imxdi: Initial supportBenoît Thébaudeau2012-09-01-0/+245
| | | | | | | | | Add support for Freescale's i.MX DryIce RTC, present on i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Add SchulerControl SC_SPS_1 platformMarek Vasut2012-09-01-0/+535
| | | | | | | | | | | This i.MX28 platform supports the following: * 2x FEC ethernet * USB on USBH0 * I2C EEPROM * SPI NVRAM * LEDs Signed-off-by: Marek Vasut <marex@denx.de>
* i.MX28: bug fixes in PMU configuration codeStathis Voukelatos2012-09-01-6/+6
| | | | | | Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com>
* MX28: Move the u-boot.bd info CPUDIR/SOCDIRMarek Vasut2012-09-01-29/+1
| | | | | | | | This gets us rid of duplication of the same file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* vision2: do not overwrite the consoleFabio Estevam2012-09-01-2/+11
| | | | | | | On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx51evk: do not overwrite the consoleFabio Estevam2012-09-01-1/+11
| | | | | | | On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: mx53loco: do not overwrite the consoleStefano Babic2012-09-01-6/+8
| | | | | | | | | On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX28: Fix MXS MMC DMA issuesMarek Vasut2012-09-01-15/+19
| | | | | | | | | | | | The DMA didn't work properly because the DMA descriptor wasn't properly cleaned after it was used once. Also, the DMA_ENABLE bit was enabled/disabled too late. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* MX28: Transfer small blocks via PIO in MXS MMCMarek Vasut2012-09-01-26/+20
| | | | | | | | | | | Large blocks (> 512b) shall be transfered via DMA to make things a bit faster. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* MX28: Split out the PIO and DMA transfer functionsMarek Vasut2012-09-01-68/+86
| | | | | | | | | | Move DMA and PIO data transfer parts into separate functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* MX28: Fix up the MMC driver DMA modeMarek Vasut2012-09-01-2/+8
| | | | | | | | | | | The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1. Also, it was using SSP0 DMA channel for all SSP devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCsOtavio Salvador2012-09-01-1/+1
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Clarify why we poweroff in case of brownout in 5v conflictOtavio Salvador2012-09-01-0/+4
| | | | | | | | If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable but this wasn't clear on code so a comment has been added to clarify it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador2012-09-01-116/+116
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-189/+188
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register acessor macros with 'mxs' prefixOtavio Salvador2012-09-01-529/+529
| | | | | | | As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: reorganize source directory for easy sharing of code in i.MXS SoCsOtavio Salvador2012-09-01-14/+14
| | | | | | | | | Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* mx28evk: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX28: use a clear name for DDR2 initializationOtavio Salvador2012-09-01-6/+6
| | | | | | | | | The mx28 prefix has been added to the initialization data and function so it is clear by which SoC it is used as i.MX233 will have a specific one. While on that, we also change it to static. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* Add support for Bluegiga APX4 Development KitVeli-Pekka Peltola2012-09-01-0/+618
| | | | | | | | | | This adds support for Bluegiga APX4 Development Kit. It is built around Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC, RTC and USB. APX4 has only one ethernet port. Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Cc: Stefano Babic <sbabic@denx.de>
* MX28: extend print_cpuinfo() to use chip informationOtavio Salvador2012-09-01-2/+40
| | | | | | | The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* MX28: SPI: Add DMA transfer supportMarek Vasut2012-09-01-1/+116
| | | | | | | | | | | | | | | | | The DMA transfers happen only if the transfered data are larger than 512 bytes. Otherwise PIO is used. This is a small speed optimization. The DMA transfer doesn't work if unaligned transfer is requested due to the limitation of the DMA controller. This has to be fixed by introducing generic bounce buffer. Therefore the DMA feature is now disabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Pull out the PIO transfer functionMarek Vasut2012-09-01-33/+41
| | | | | | | | | | | Pull out all the PIO transfer logic into separate function, so DMA can be added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Refactor spi_xfer a bitMarek Vasut2012-09-01-10/+22
| | | | | | | | | | This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
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