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* spi: xilinx_spi: Perform software reset during slave setupJason Wu2013-02-04-0/+5
| | | | | | to make sure it is in the clear state. Signed-off-by: Jason Wu <huanyu@xilinx.com>
* common: cmd_bdinfo: Fix bdinfo to show all MACs for Microblaze and ARMMichal Simek2013-02-04-4/+21
| | | | | | | - Show all ethernet MACs in the system. - Show current ethernet device Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Add muldi3.c which contains routines for _muldi3David Holsgrove2013-02-04-0/+92
| | | | | | | | | | | | | | | | | | | Referenced arch/blackfin/lib/muldi3.c and the linux kernel. Resolves issue seen when building u-boot for HW_MUL=0; PLATFORM_CPPFLAGS += -mxl-soft-mul PLATFORM_CPPFLAGS += -mno-xl-multiply-high which resulted in error while linking to libgcc.a without mul hw (bs / m); libgcc.a(_muldi3.o): In function `__muldi3': .... src/gcc-4.6.2/libgcc/libgcc2.c:550: undefined reference to `_GLOBAL_OFFSET_TABLE_' This link failure would not occur if we used gcc instead of ld directly, as gcc will correctly use the crt's to resolve this link. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* block: systemace: Added missing "else" in "ace_writew"Alexey Brodkin2013-02-04-2/+2
| | | | | | | | | | | | | | | System ACE compact flash controller supports either 8-bit (default) or 16-bit data transfers. And in corresponding driver we need to implement read/write of 16-bit data words properly for both modes of operation. In existing code if width==8 both branches get executed which may cause unexpected behavior of SystemAce controller. Addition of "else" fixes described issue and execution is done as expected for both (8-bit and 16-bit) data bus widths. Signed-off-by: Alexey Brodkin <alexey.brodkin@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* vfat: Fix mkcksum argument sizesMarek Vasut2013-01-31-2/+2
| | | | | | | | | | | | | | | | In case a function argument is known/fixed size array in C, the argument is still decoyed as pointer instead ( T f(U n[k]) ~= T fn(U *n) ) and therefore calling sizeof on the function argument will result in the size of the pointer, not the size of the array. The VFAT code contains such a bug, this patch fixes it. Reported-by: Aaron Williams <Aaron.Williams@cavium.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <tom.rini@gmail.com> Cc: Aaron Williams <Aaron.Williams@cavium.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach2013-01-30-1/+1
| | | | | | | | | No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-01-30-437/+76
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| * MIPS: qi_lb60: remove custom u-boot.lds scriptGabor Juhos2013-01-31-61/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. The qi_lb60 target produces a slightly different image after the change than before. The value of 'num_got_entries' symbol is different: @@ -49,7 +49,7 @@ 801000b4: 80122d00 lb s2,11520(zero) 801000b8: 80123500 lb s2,13568(zero) 801000bc: 80123ef8 lb s2,16120(zero) -801000c0: 00000139 0x139 +801000c0: 00000136 tne zero,zero,0x4 801000c4 <in_ram>: 801000c4: 8d0bfffc lw t3,-4(t0) This is caused by the different placement of the '__got_start' and '__got_end' symbols between the board specific scrip and the unified script. board specific script: __got_start = .; .got : { *(.got) } __got_end = .; unified script: .got : { __got_start = .; *(.got) __got_end = .; } Despite this difference, the resulting images are functionally identical. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: dbau1x00: remove custom u-boot.lds scriptGabor Juhos2013-01-31-65/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All dbau1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: incaip: remove custom u-boot.lds scriptGabor Juhos2013-01-31-65/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All incaip targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de>
| * MIPS: vct: remove custom u-boot.lds scriptGabor Juhos2013-01-31-68/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All vct targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: pb1x00: remove custom u-boot.lds scriptGabor Juhos2013-01-31-65/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All pb1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: qemu-mips: use the unified u-boot.lds scriptGabor Juhos2013-01-31-70/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All qemu_mips targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: add unified u-boot.lds fileGabor Juhos2013-01-31-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Stefan Roese <sr@denx.de>
| * MIPS: remove OUTPUT_FORMAT from linker scriptsGabor Juhos2013-01-30-23/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: xburst: simplify relocation offset calculationGabor Juhos2013-01-30-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: simplify relocated _G_O_T_ address calculationGabor Juhos2013-01-30-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: start.S: don't save flush_cache parameters in advanceGabor Juhos2013-01-27-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Saving the parameters in advance unnecessarily complicates the code. The destination address is already saved in the 's2' register, and that register is not clobbered by the copy loop. The size of the copied data can be computed after the copy loop is done. Change the code to compute the size parameter right before calling flush_cache, and set the destination address parameter in the delay slot of the actuall call. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: simplify relocation offset calculationGabor Juhos2013-01-27-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: save reused arguments earlier in relocate_codeGabor Juhos2013-01-27-4/+6
| | | | | | | | | | | | | | | | | | Save the reused parameters at the beginning of the 'relocate_code' function. This makes the function a bit more readable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: set sp register directlyGabor Juhos2013-01-27-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses two instructions to load the stack pointer into the 'sp' register. This results in the following assembly code: 468: 3c088040 lui t0,0x8040 46c: 251d0000 addiu sp,t0,0 The first instuction loads the stack pointer into the 't0' register then the value of the 'sp' register is computed by adding zero to the value of the 't0' register. The same issue present on the 64-bit version as well: 56c: 3c0c8040 lui t0,0x8040 570: 659d0000 daddiu sp,t0,0 Change the code to load the stack pointer directly into the 'sp' register. The generated code is functionally equivalent to the previous version but it is simpler. 32-bit: 468: 3c1d8040 lui sp,0x8040 64-bit: 56c: 3c1d8040 lui sp,0x8040 Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: fix boundary check in relocate_codeGabor Juhos2013-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The loop code copies more data with one than necessary due to the 'ble' instuction. Use the 'blt' instruction instead to fix that. Due to the lack of suitable hardware the Xburst specific code is compile tested only. However the change is quite obvious. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start{, 64}.S: fill branch delay slots with NOP instructionsGabor Juhos2013-01-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: convert IO port accessor functions to 'static inline'Gabor Juhos2013-01-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The currently used 'extern inline' directive causes the following compiler warnings if CONFIG_SWAP_IO_SPACE is defined: <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: use inline directive for __in*s functionsGabor Juhos2013-01-22-1/+1
| | | | | | | | | | | | | | | | | | All other IO accessor functions are using the 'inline' directive. Use that also for the __in*s to make it consistent with the other variants. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | corenet: Disable video on P2020DSAndy Fleming2013-01-30-1/+1
| | | | | | | | | | | | | | | | The P2020DS build had grown too large, and video support isn't enabled in almost any other Freescale board. Disabling it allows us to keep building, and provides options for reenabling it later. Signed-off-by: Andy Fleming <afleming@freescale.com>
* | board/common: Add support for QIXIS read/write using i2cPrabhakar Kushwaha2013-01-30-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | QIXIS FPGA is accessable via both i2c and flash controller. Only flash controller access is supported. Add support of i2c based access. It is quite useful in the scenario where either flash controller path is broken or not present. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu2013-01-30-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg2013-01-30-1/+92
| | | | | | | | | | | | | | | | | | | | If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUEAnatolij Gustschin2013-01-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in the board config file doesn't work and memory is always initialized to the value 0xdeadbeef. Only use this default value if a board doesn't define CONFIG_MEM_INIT_VALUE. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-24/+49
| | | | | | | | | | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/85xx: Add BSC9132QDS supportPrabhakar Kushwaha2013-01-30-0/+1618
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha2013-01-30-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commandsJames Yang2013-01-30-11/+47
| | | | | | | | | | | | | | | | | | | | | | This patch adds the ability for the FSL DDR interactive debugger to automatically run the sequence of commands stored in the ddr_interactive environment variable. Commands are separated using ';'. ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | README.fsl-ddr typos and update to reflect hotkeyJames Yang2013-01-30-14/+21
| | | | | | | | | | | | | | | | Documentation fix to README.fsl-ddr to fix typos and to reflect use of 'd' hotkey to enter the FSL DDR debugger. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Add copy command to FSL DDR interactiveJames Yang2013-01-30-0/+132
| | | | | | | | | | | | | | | | | | Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Fix data stage name matching issueJames Yang2013-01-30-1/+2
| | | | | | | | | | | | | | | | | | | | This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Move DDR command parsing to separate functionJames Yang2013-01-30-79/+74
| | | | | | | | | | | | | | | | Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun2013-01-30-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDBValentin Longchamp2013-01-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | In order to be able to build a u-boot.pbl image, both the CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be defined. This patch sets these two files for the P2041RDB board. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/p2041: add RCW file for P2041RDBValentin Longchamp2013-01-30-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board. This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/t4240qds: Print FPGA detail versionPrabhakar Kushwaha2013-01-30-2/+9
| | | | | | | | | | | | | | | | | | | | | | Qixis FPGA has tag data contains image name and build date. It is helpful to identify the FPGA image precisely. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/t4240qds: Add support to dump switch settings on t4240qds boardShaveta Leekha2013-01-30-0/+60
| | | | | | | | | | | | | | | | | | | | This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/b4860qds: Add support to dump switch settings on b4860qds boardShaveta Leekha2013-01-30-0/+47
| | | | | | | | | | | | | | | | | | | | This function is called by "qixis_reset switch" command and switch settings are calculated from FPGA/qixis registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/qixis: enable qixis dump command and add switch dumping commandShaveta Leekha2013-01-30-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/b4860qds: Added Support for B4860QDSYork Sun2013-01-30-0/+2536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor. B4860QDS Overview ------------------ - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB of memory in two ranks of 2 GB. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch VSC3316 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. - B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for AMC mode. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The RCW source is set by appropriate DIP-switches: - 16-bit NOR Flash / PROMJet - QIXIS 8-bit NOR Flash Emulator - 8-bit NAND Flash - 24-bit SPI Flash - Long address I2C EEPROM - Available debug interfaces are: - On-board eCWTAP controller with ETH and USB I/F - JTAG/COP 16-pin header for any external TAP controller - External JTAG source over AMC to support B2B configuration - 70-pin Aurora debug connector - QIXIS (FPGA) logic: - 2 KB internal memory space including - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1, 2 and RTCCLK. - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks - total four refclk, including CPRI clock scheme Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha2013-01-30-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | board/freescale/common:Add support of QTAG registerPrabhakar Kushwaha2013-01-30-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE fields. These fields have FPGA build version, image name and build date information. Add support to parse these fields to have complete FPGA image information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-1/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-1/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-05 13:49:54 +0000