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* MPC8544DS: Update config.hKumar Gala2008-06-11-1/+1
| | | | | | | * Enable flash progress * remove CLEAR_LAW0 since we dont really use it Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove unused and unconfigured memory test code.Kumar Gala2008-06-11-275/+0
| | | | | | | Remove unused and unconfigured DDR test code from FSL 85xx boards. Besides, other common code exists. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Socrates: Added FPGA base address update in FDT.Sergei Poselenov2008-06-11-0/+10
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: NAND support added. Changed the U-Boot base address andSergei Poselenov2008-06-11-4/+227
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* NAND: Added support for 128-bit OOB, adaptedSergei Poselenov2008-06-11-14/+34
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: added missed file with UPMA configuration data.Sergei Poselenov2008-06-11-0/+55
| | | | Signed-of-by: Sergei Poselenov <sposelenov@emcraft.com>
* Socrates: Added FPGA mapping. LAWs and TLBs cleanup.Sergei Poselenov2008-06-11-30/+27
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-11-0/+70
| | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Socrates: config file cleanup.Sergei Poselenov2008-06-11-9/+3
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* TQM85xx: Change memory map to support Flash memory > 128 MiBWolfgang Grandegger2008-06-11-11/+167
| | | | | | | | | | | | | | | | | Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: NAND support via local bus UPMBWolfgang Grandegger2008-06-11-8/+558
| | | | | | | | | | | | | | | | | | | This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. It is now based on the re-written FSL NAND UPM driver. A patch has been posted earlier today with the subject: "NAND FSL UPM: driver re-write using the hwcontrol callback" Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time. Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM8548: PCI express supportWolfgang Grandegger2008-06-11-36/+249
| | | | | | | | | This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM8548: Basic support for the TQM8548 modulesWolfgang Grandegger2008-06-11-33/+334
| | | | | | | | | | | | This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4 Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Flat Device TreeWolfgang Grandegger2008-06-11-13/+64
| | | | | | | | This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Support for Intel 82527 compatible CAN controllerWolfgang Grandegger2008-06-10-0/+73
| | | | | | | | This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Bugfix in the SDRAM initialisationWolfgang Grandegger2008-06-10-1/+3
| | | | | | | The CS0_BNDS register is now set according to the detected memory size. Signed-off-by Martin Krause <martin.krause@tqs.de>
* TQM85xx: Fix chip select configuration for second FLASH bankWolfgang Grandegger2008-06-10-38/+46
| | | | | | | This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks. Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Support for Spansion 'N' type flashes addedWolfgang Grandegger2008-06-10-4/+16
| | | | | | | | | | | The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors, than the formerly used 'M' types (S29GLxxxM series), so the flash layout needs to be changed -> new start address of the environment. The macro definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be defined for boards with 'N' type flashes. Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM85xx: Fix CPM port pin configurationWolfgang Grandegger2008-06-10-0/+6
| | | | | | | | | Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG). Signed-off-by: Martin Krause <martin.krause@tqs.de>
* TQM85xx: Various coding style fixesWolfgang Grandegger2008-06-10-291/+293
| | | | Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* socrates: Fix PCI clk fix patchAndy Fleming2008-06-10-1/+3
| | | | | | | | | The submitted patch seems to have been more up-to-date, but an older patch was already in the repository. This patch encompasses the differences Taken entirely from Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* NAND FSL UPM: driver re-write using the hwcontrol callbackWolfgang Grandegger2008-06-10-83/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a re-write of the NAND FSL UPM driver using the more universal hwcontrol callback (instead of the cmdfunc callback). Here is a brief list of furher modifications: - For the time being, the UPM setup writing the UPM array has been removed from the driver and must now be done by the board specific code. - The bus width definition in "struct fsl_upm_nand" is now in bits to comply with the corresponding Linux driver and 8, 16 and 32 bit accesses are supported. - chip->dev_read is only set if fun->dev_ready != NULL, which is required for boards not connecting the R/B pin. - A few issue have been fixed with MxMR bit manipulation like in the corresponding Linux driver. Note: I think the "io_addr" field of "struct fsl_upm" could be removed as well, because the address is already determined by "nand->IO_ADDR_[RW]", but I'm not 100% sure. This patch has been tested on a TQM8548 modules with the NAND chip Micron MT29F8G08FABWP. This patch is based on the following patches posted to this list a few minutes ago: PPC: add accessor macros to clear and set bits in one shot 83xx/85xx/86xx: add more MxMR local bus definitions Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger2008-06-10-9/+11
| | | | | | | | | | The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* PPC: add accessor macros to clear and set bits in one shotWolfgang Grandegger2008-06-10-0/+36
| | | | | | | | | | | | | PPC: add accessor macros to clear and set bits in one shot This patch adds macros from linux/include/asm-powerpc/io.h to clear and set bits in one shot using the in_be32, out_be32, etc. accessor functions. They are very handy to manipulate bits it I/O registers. This patch is required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* TQM: move TQM boards to board/tqcWolfgang Grandegger2008-06-10-15/+15
| | | | | | | Move all TQM board directories to the vendor specific directory "tqc" for modules from TQ-Components GmbH (http://www.tqc.de). Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 83xx/85xx/86xx: add more MxMR local bus definitionsWolfgang Grandegger2008-06-10-5/+38
| | | | | | | | | | | | | | | | | | | | 83xx/85xx/86xx: add more MxMR local bus definitions This patch adds more macro definitions for the UPM Machine Mode Registers They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx common local bus definitions into include/asm-ppc/fsl_lbc.h. They are required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. This patch is based on the following two patches from Anton Vorontsov: http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html I leave coding style violation fixes, code beautification and name corrections to somebody else ;-(. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 83xx/85xx: further localbus cleanupsAnton Vorontsov2008-06-10-45/+23
| | | | | | | Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.hAnton Vorontsov2008-06-10-233/+256
| | | | | | | This patch moves Freescale Localbus defines out of mpc83xx.h, so we could use it on MPC85xx and MPC86xx processors. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 85xx: Add setting of cache props in the device tree.Kumar Gala2008-06-10-0/+128
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: expose cpu identificationKumar Gala2008-06-10-36/+51
| | | | | | | | | | | | | The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define itKumar Gala2008-06-09-2/+6
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-09-3/+5
| | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/masterWolfgang Denk2008-06-05-1279/+8590
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| * Socrates: Fix PCI bus frequency reportWolfgang Denk2008-06-03-3/+13
| | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * Fix incorrect switch for IF_TYPE in part.cTor Krill2008-06-03-2/+2
| | | | | | | | | | | | | | | | | | Use correct field in block_dev_desc_t when writing interface type in dev_print. Error introduced in 574b3195. Also added fix from Martin Krause Signed-off-by: Tor Krill <tor@excito.com>
| * Add size #defines for Altera Cyclone-II EP2C8 and EP2C20.Andre Schwarz2008-06-03-0/+2
| | | | | | | | Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
| * Additional fix to readline_into_buffer() with CONFIG_CMDLINE_EDITING before ↵Peter Tyser2008-06-03-6/+0
| | | | | | | | | | | | | | | | | | | | | | relocating Removed unneeded command line history initialization. Also, the original code would access the 'initted' variable before relocation to SDRAM which resulted in erratic behavior since the bss is not initialized when executing from flash. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * PPC4xx: Simplified post_word_{load, store}Grant Erickson2008-06-03-15/+11
| | | | | | | | | | | | | | This patch simplifies post_word_{load,store} by using the preprocessor to eliminate redundant, copy-and-pasted code. Signed-off-by: Grant Erickson <gerickson@nuovations.com>
| * DTT: Issue one-shot command on AD7414 (LM75 code) to read tempStefan Roese2008-06-03-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On AD7414 the first value upon bootup is not read correctly. This is most likely because of the 800ms update time of the temp register in normal update mode. To get current values each time we issue the "dtt" command including upon powerup we switch into one-short mode. This patch fixes the problem on AD7414 equipped boards (Sequoia, Canyonlands etc), that temp value printed in the bootup log was incorrect. Signed-off-by: Stefan Roese <sr@denx.de>
| * Add support for environment in SPI flashHaavard Skinnemoen2008-06-03-2/+136
| | | | | | | | | | | | | | | | | | This is pretty incomplete...it doesn't handle reading the environment before relocation, it doesn't support redundant environment, and it doesn't support embedded environment. But apart from that, it does seem to work. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * SPI Flash: Add "sf" commandHaavard Skinnemoen2008-06-03-0/+192
| | | | | | | | | | | | | | | | This adds a new command, "sf" which can be used to manipulate SPI flash. Currently, initialization, reading, writing and erasing is supported. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * SPI Flash subsystemHaavard Skinnemoen2008-06-03-0/+688
| | | | | | | | | | | | | | | | | | | | This adds a new SPI flash subsystem. Currently, only AT45 DataFlash in non-power-of-two mode is supported, but some preliminary support for other flash types is in place as well. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * SPI API improvementsHaavard Skinnemoen2008-06-03-209/+584
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
| * Move definition of container_of() to common.hHaavard Skinnemoen2008-06-03-22/+11
| | | | | | | | | | | | | | | | | | | | | | AVR32 and AT91SAM9 both have their own identical definitions of container_of() taken from the Linux kernel. Move it to common.h so that all architectures can use it. container_of() is already used by some drivers, and will be used extensively by the new and improved SPI API. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * soft_i2c: Pull SDA high before readingHaavard Skinnemoen2008-06-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Spotted by Dean Capindale. Systems that support open-drain GPIO properly are allowed provide an empty I2C_TRISTATE define. However, this means that we need to be careful not to drive SDA low when the slave is expected to respond. This patch adds a missing I2C_SDA(1) to read_byte() required to tristate the SDA line on systems that support open-drain GPIO. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * Fix warnings from gcc-4.3.0 build on a ppc hostKumar Gala2008-06-03-1/+3
| | | | | | | | | | | | | | | | | | | | | | * The cfi_flash.c memset fix actual allows the board to boot so there is a bit more going on here than just resolving warnings associated with uninitialized variables. * include/asm/bitops.h:302: warning: '__swab32p' is static but used in inline function 'ext2_find_next_zero_bit' which is not static Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * MPC512x: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-03-1/+7
| | | | | | | | | | | | | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * Make sure common.h is the first include.Kumar Gala2008-06-03-1/+2
| | | | | | | | | | | | | | | | | | If common.h isn't first we can get CONFIG_ options defined in the board config file ignored. This can cause an issue if any of those config options impact the size of types of data structures (eg CONFIG_PHYS_64BIT). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Avoid initrd and logbuffer area overlapsMarian Balakowicz2008-06-03-1/+25
| | | | | | | | | | | | | | | | | | Add logbuffer to reserved LMB areas to prevent initrd allocation from overlaping with it. Make sure to use correct logbuffer base address. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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