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* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2014-08-29-328/+417
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| * sunxi: dram: Autodetect DDR3 bus width and densitySiarhei Siamashka2014-08-12-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case if the 'dram_para' struct does not specify the exact bus width or chip density, just use a trial and error method to find a usable configuration. Because all the major bugs in the DRAM initialization sequence are now hopefully fixed, it should be safe to re-initialize the DRAM controller multiple times until we get it configured right. The original Allwinner's boot0 bootloader also used a similar autodetection trick. The DDR3 spec contains the package pinout and addressing table for different possible chip densities. It appears to be impossible to distinguish between a single chip with 16 I/O data lines and a pair of chips with 8 I/O data lines in the case if they provide the same storage capacity. Because a single 16-bit chip has a higher density than a pair of equivalent 8-bit chips, it has stricter refresh timings. So in the case of doubt, we assume that 16-bit chips are used. Additionally, only Allwinner A20 has all A0-A15 address lines and can support densities up to 8192. The older Allwinner A10 and Allwinner A13 can only support densities up to 4096. We deliberately leave out DDR2, dual-rank configurations and the special case of a 8-bit chip with density 8192. None of these configurations seem to have been ever used in real devices. And no new devices are likely to use these exotic configurations (because only up to 2GB of RAM can be populated in any case). This DRAM autodetection feature potentially allows to have a single low performance fail-safe DDR3 initialiazation for a universal single bootloader binary, which can be compatible with all Allwinner A10/A13/A20 based devices (if the ifdefs are replaced with a runtime SoC type detection). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Derive write recovery delay from DRAM clock speedSiarhei Siamashka2014-08-12-1/+16
| | | | | | | | | | | | | | | | | | | | | | The write recovery time is 15ns for all JEDEC DDR3 speed bins. And instead of hardcoding it to 10 cycles, it is possible to set tighter timings based on accurate calculations. For example, DRAM clock frequencies up to 533MHz need only 8 cycles for write recovery. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memorySiarhei Siamashka2014-08-12-22/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the known Allwinner A10/A13/A20 devices are using just single rank DDR3 memory. So don't pretend that we support DDR2 or more than one rank, because nobody could ever test these configurations for real and they are likely broken. Support for these features can be added back in the case if such hardware actually exists. As part of this code cleanup, also replace division by 1024 with division by 1000 for the refresh timing calculations. This allows to use the original non-skewed tRFC timing table from the DRR3 spec and make code less confusing. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Configurable DQS gating window mode and delaySiarhei Siamashka2014-08-12-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware DQS gate training is a bit unreliable and does not always find the best delay settings. So we introduce a 32-bit 'dqs_gating_delay' variable, where each byte encodes the DQS gating delay for each byte lane. The delay granularity is 1/4 cycle. Also we allow to enable the active DQS gating window mode, which works better than the passive mode in practice. The DDR3 spec says that there is a 0.9 cycles preamble and 0.3 cycle postamble. The DQS window has to be opened during preamble and closed during postamble. In the passive window mode, the gating window is opened and closed by just using the gating delay settings. And because of the 1/4 cycle delay granularity, accurately hitting the 0.3 cycle long postamble is a bit tough. In the active window mode, the gating window is auto-closing with the help of monitoring the DQS line, which relaxes the gating delay accuracy requirements. But the hardware DQS gate training is still performed in the passive window mode. It is a more strict test, which is reducing the results variance compared to the training with active window mode. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'Siarhei Siamashka2014-08-12-14/+16
| | | | | | | | | | | | | | | | It is going to be useful in more than one place. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Improve DQS gate data training error handlingSiarhei Siamashka2014-08-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | The stale error status should be cleared for all sun4i/sun5i/sun7i hardware and not just for sun7i. Also there are two types of DQS gate training errors ("found no result" and "found more than one possible result"). Both are handled now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Use divisor P=1 for PLL5Siarhei Siamashka2014-08-12-17/+11
| | | | | | | | | | | | | | | | | | | | | | This configures the PLL5P clock frequency to something in the ballpark of 1GHz and allows more choices for MBUS and G2D clock frequency selection (using their own divisors). In particular, it enables the use of 2/3 clock speed ratio between MBUS and DRAM. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)Siarhei Siamashka2014-08-12-14/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed. Allwinner A13 uses only 16-bit data bus width to connect the external DRAM, which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so it does not make much sense to clock a wider internal bus at a very high speed. The Allwinner A13 manual specifies 300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer sun7i hardware (Allwinner A20) has a full width 32-bit external memory interface again, but still keeps the MBUS clock speed configurable. Clocking MBUS too low inhibits memory performance and one has to find the optimal MBUS/DRAM clock speed ratio, which may depend on many factors: http://linux-sunxi.org/A10_DRAM_Controller_Performance This patch introduces a new 'mbus_clock' parameter for the 'dram_para' struct and uses it as a desired MBUS clock speed target. If 'mbus_clock' is not set, 300 MHz is used by default to match the older hardcoded settings. PLL5P and PLL6 are both evaluated as possible clock sources. Preferring the one, which can provide higher clock frequency that is lower or equal to the 'mbus_clock' target. In the case of a tie, PLL5P has higher priority. Attempting to set the MBUS clock speed has no effect on sun4i, but does no harm either. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Re-introduce the impedance calibration ond ODTSiarhei Siamashka2014-08-12-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM controller allows to configure impedance either by using the calibration against an external high precision 240 ohm resistor, or by skipping the calibration and loading pre-defined data. The DRAM controller register guide is available here: http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0 The new code supports both of the impedance configuration modes: - If the higher bits of the 'zq' parameter in the 'dram_para' struct are zero, then the lowest 8 bits are used as the ZPROG value, where two divisors encoded in lower and higher 4 bits. One divisor is used for calibrating the termination impedance, and another is used for the output impedance. - If bits 27:8 in the 'zq' parameters are non-zero, then they are used as the pre-defined ZDATA value instead of performing the ZQ calibration. Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS lines individually. Enabling ODT for both DQ and DQS means that the 'odt_en' parameter needs to be set to 3. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functionsSiarhei Siamashka2014-08-12-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | The old 'await_completion' function is not sufficient, because in some cases we want to wait for bits to be cleared, and in the other cases we want to wait for bits to be set. So split the 'await_completion' into two new 'await_bits_clear' and 'await_bits_set' functions. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7iSiarhei Siamashka2014-08-12-11/+0
| | | | | | | | | | | | | | | | | | | | | | The older differences were likely justified by the need to mitigate the CKE delay timing violations on sun4i/sun5i. The CKE problem is already resolved, so now we can use the sun7i variant of this code everywhere. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Remove broken impedance and ODT configuration codeSiarhei Siamashka2014-08-12-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can safely remove it, because none of the currently supported boards uses these features. The existing implementation had multiple problems: - unnecessary code duplication between sun4i/sun5i/sun7i - ZQ calibration was never initiated explicitly, and could be only triggered by setting the highest bit in the 'zq' parameter in the 'dram_para' struct (this was never actually done for any of the known Allwinner devices). - even if the ZQ calibration could be started, no attempts were made to wait for its completion, or checking whether the default automatically initiated ZQ calibration is still in progress - ODT was only ever enabled on sun4i, but not on sun5i/sun7i Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There are some hints in the Rockchip Linux kernel sources, indicating that these bits are related to the automatic I/O power down feature, which is poorly understood on sunxi hardware at the moment. Avoiding to set these bits on sun4i too does not seem to have any measurable/visible impact. The impedance and ODT configuration code will be re-introdeced in one of the next comits. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Fix CKE delay handling for sun4i/sun5iSiarhei Siamashka2014-08-12-7/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires to wait for additional 500 us after the RESET pin is de-asserted. The DRAM controller takes care of this delay by itself, using a configurable counter in the SDR_IDCR register. This works in the same way on sun4i/sun5i/sun7i hardware (even the default register value 0x00c80064 is identical). Except that the counter is ticking a bit slower on sun7i (3 DRAM clock cycles instead of 2), resulting in longer actual delays for the same settings. This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i SoC variants and not just for sun7i alone. Also an explicit udelay(500) is added immediately after DDR3 reset for extra safety. This is a duplicated functionality. But since we don't have perfect documentation, it may be reasonable to play safe. Half a millisecond boot time increase is not that significant. Boot time can be always optimized later. Preferebly by the people, who have the hardware equipment to check the actual signals on the RESET and CKE lines and verify all the timings. The old code did not configure the SDR_IDCR register for sun4i/sun5i, but performed the DDR3 reset very early for sun4i/sun5i. This resulted in a larger time gap between the DDR3 reset and the DDR3 initialization steps and reduced the chances of CKE delay timing violation to cause real troubles. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Respect the DDR3 reset timing requirementsSiarhei Siamashka2014-08-12-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The RESET pin needs to be kept low for at least 200 us according to the DDR3 spec. So just do it the right way. This issue did not cause any visible major problems earlier, because the DRAM RESET pin is usually already low after the board reset. And the time gap before reaching the sunxi u-boot DRAM initialization code appeared to be sufficient. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Remove broken super-standby remnantsSiarhei Siamashka2014-08-12-46/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this means that DRAM is currently in self-refresh mode and retaining the old data. Since we have no idea what to do in this situation yet, just set this register to 0 and initialize DRAM in the same way as on any normal reboot (discarding whatever was stored there). This part of code was apparently used by the Allwinner boot0 bootloader to handle resume from the so-called super-standby mode. But this particular code got somehow mangled on the way from the boot0 bootloader to the u-boot-sunxi bootloader and has no chance of doing anything even remotely sane. For example: 1. in the original boot0 code we had "mctl_write_w(SDR_DPCR, 0x16510000)" (write to the register) and in the u-boot it now looks like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the register) 2. in the original boot0 code it was issuing three commands "0x12, 0x17, 0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry, Self-Refresh entry, Refresh) Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dram: Remove useless 'dramc_scan_dll_para()' functionSiarhei Siamashka2014-08-12-124/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()' function by trying different DLL adjustments and using the hardware DQS gate training result as a feedback is a great source of inspiration, but it just can't work properly the way it is implemented now. The fatal problem of this implementation is that the DQS gating window can be successfully found for almost every DLL delay adjustment setup that gets tried. Thus making it unable to see any real difference between 'good' and 'bad' settings. Also this code was supposed to be only activated by setting the highest bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram configuration). But none of the linux-sunxi devices has ever used it for real. Basically, this code is just a dead weight. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add environment settings to make extlinux.conf booting workHans de Goede2014-08-12-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | Automatic booting using an extlinux.conf file requires various environment variables to be set. Also modify CONFIG_SYS_LOAD_ADDR and CONFIG_STANDALONE_LOAD_ADDR to match the value chosen for kernel_addr_r, see the added comment for why the new value is chosen. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * sunxi-common.h: Use new generic $bootcmdHans de Goede2014-08-12-3/+22
| | | | | | | | | | | | | | Use the new standard bootcmd from <config_distro_bootcmd.h>. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * config: introduce a generic $bootcmdDennis Gilmore2014-08-12-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This generic $bootcmd, and associated support macros, automatically searches a defined set of storage devices (or network protocols) for an extlinux configuration file or U-Boot boot script in various standardized locations. Distros that install such a boot config file/script in those standard locations will get easy-to-set-up booting on HW that enables this generic $bootcmd. Boards can define the set of devices from which boot is attempted, and the order in which they are attempted. Users may later customize this set/order by edting $boot_targets. Users may interrupt the boot process and boot from a specific device simply by executing e.g.: $ run bootcmd_mmc1 or: $ run bootcmd_pxe This patch was originally written by Dennis Gilmore based on Tegra and rpi_b boot scripts. I have made the following modifications since then: * Boards must define the BOOT_TARGET_DEVICES macro in order to specify the set of devices (and order) from which to attempt boot. If needed, we can define a default directly in config_distro_bootcmd.h. * Removed $env_import and related variables; nothing used them, and I think it's better for boards to pre-load an environment customization file using CONFIG_PREBOOT if they need. * Renamed a bunch of variables to suit my whims:-) Signed-off-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Simon Glass <sjg@chromium.org>
| * sunxi: Kconfig: move common settings into a shared code blockHans de Goede2014-08-12-26/+6
| | | | | | | | | | | | | | | | SYS_CPU, SYS_BOARD and SYS_SOC are identical for all sunxi boards, move them to a shared code block. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi-common.h: Don't undef CONFIG_CMD_NET only to redefine it again laterHans de Goede2014-08-12-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | config_distro_defaults.h which is include later will redefine CONFIG_CMD_NET, drop the useless / meaningless undef of it. While at also move the undef of CONFIG_CMD_FPGA up to directly under the include of config_cmd_defaults.h, to make it clear that it overwrites the setting done from config_cmd_defaults.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi-common.h: Don't undefine CONFIG_CMD_NFSHans de Goede2014-08-12-1/+0
| | | | | | | | | | | | | | | | I see no reason to override the choice to include this from config_cmd_defauls.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi-common.h: Remove dead #ifdef CONFIG_CMD_NET code blockHans de Goede2014-08-12-8/+0
| | | | | | | | | | | | | | | | | | We undef CONFIG_CMD_NET at line 167, and there is nothing re-defining it between line 167 and the #ifdef CONFIG_CMD_NET, so remove this effectively dead block. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi-common.h: Remove CONFIG_SYS_BOOT_GET_CMDLINEHans de Goede2014-08-12-2/+0
| | | | | | | | | | | | | | | | sunxi does not need this and it should never have been enabled for it in the first place. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | README.kconfig: document backward compatibility "make *_config"Masahiro Yamada2014-08-28-0/+8
| | | | | | | | | | | | | | | | | | | | Commit 3ff291f371fa9858426774f3732924bacb61ed1c (kconfig: convert Kconfig helper script into a shell script) restored "<board>_config" target for backward compatibility. It should be documented. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | tools/genboardscfg.py: change shebang into /usr/bin/env python2Masahiro Yamada2014-08-28-1/+3
| | | | | | | | | | | | | | | | | | This tool only works on python 2 (python 2.6 or lator). Change the shebang to make sure the script is run by python 2 and clearly say the supported version in the comment block. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | net: cpsw: am335x: Drop constant link checking from rx/tx path'sStefan Roese2014-08-28-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected to the CPSW MAC) that the network performance in U-Boot is quite poor. Only when the transfer is started without a cable connected, and the cable is plugged after the first timeout "T" occured, an increased in performance can be seen. Debugging has revealed, that the cpsw driver has constant link checking builtin into the rx and tx functions. This results in the bad performance and seems to be unnecessary. The link has already been checked in the init function, before the transfer is started. This usually is sufficient. BTW: I have seen no other network driver in U-Boot so far, that constantly checks for link in the rx / tx functions. The performance numbers on the DXR2 board are: 0.56 MiB/s cpsw_check_link() in rx and tx path 0.87 MiB/s cpsw_check_link() only in tx path 1.0 MiB/s cpsw_check_link() only in rx path 2.7 MiB/s no cpsw_check_link() in rx and tx path So with this patch the network performance on DXR2 increases from 0.56 to 2.7 MiB/s (nearly 5 times as fast). Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Samuel Egli <samuel.egli@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
* | tools/genboardscfg.py: improve performanceMasahiro Yamada2014-08-28-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I guess some developers are already getting sick of this tool because it generally takes a few minites to generate the boards.cfg on a reasonable computer. The idea popped up on my mind was to skip Makefiles and to run script/kconfig/conf directly. This tool should become about 4 times faster. You might still not be satisfied, but better than doing nothing. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: check if the boards.cfg is up to dateMasahiro Yamada2014-08-28-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks silly to regenerate the boards.cfg even when it is already up to date. The tool should exit with doing nothing if the boards.cfg is newer than any of defconfig, Kconfig and MAINTAINERS files. Specify -f (--force) option to get the boards.cfg regenerated regardless its time stamp. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: fix minor problems on terminationMasahiro Yamada2014-08-28-66/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tool deletes the incomplete boards.cfg if it encounters an error or is is terminated by the user. I notice some problems even though they rarely happen. [1] The boards.cfg is removed if the program is terminated during __gen_boards_cfg() function but before boards.cfg is actually touched. In this case, the previous boards.cfg should be kept as it is. [2] If an error occurs while deleting the incomplete boards.cfg, the program throws another exception. This hides the privious exception and we will not be able to know the real cause. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: wait for unfinished subprocesses before error-outMasahiro Yamada2014-08-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an error occurs or the program is terminated by the user on the way, the destructer __del__ of class Slot is invoked and the work directories are removed. We have to make sure there are no subprocesses (in this case, "make O=<work_dir> ...") using the work directories before removing them. Otherwise the subprocess spits a bunch of error messages possibly causing more problems. Perhaps some users may get upset to see too many error messages. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: be tolerant of insane KconfigMasahiro Yamada2014-08-28-2/+9
| | | | | | | | | | | | | | | | | | | | The tools/genboardscfg.py expects all the Kconfig and defconfig are written correctly. Imagine someone accidentally has broken a board. Error-out just for one broken board is annoying for the other developers. Let the tool skip insane boards and continue processing. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: be tolerant of missing MAINTAINERSMasahiro Yamada2014-08-28-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | tools/genboardscfg.py expects all the boards have MAINTAINERS. If someone adds a new board but misses to add its MAINTAINERS file, tools/genboardscfg.py fails to generate the boards.cfg file. It is annoying for the other developers. This commit allows tools/genboardscfg.py to display warning messages and continue processing even if some MAINTAINERS files are missing or have broken formats. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | tools/genboardscfg.py: ignore defconfigs starting with a dotMasahiro Yamada2014-08-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Kconfig in U-Boot creates a temporary file configs/.tmp_defconfig during processing "make <board>_defconfig". The temporary file might be left over for some reasons. Just in case, tools/genboardscfg.py should make sure to not read such garbage files. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Correct sandbox filesystem commands in FIT image testSimon Glass2014-08-28-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The host filesystem name has changed, so update the tests. The tests now run again correctly: $ make O=b/sandbox sandbox_defconfig all ... $ test/image/test-fit.py -u b/sandbox/u-boot FIT Tests ========= Kernel load Kernel + FDT load Kernel + FDT + Ramdisk load Tests passed Caveat: this is only a sanity check - test coverage is poor Signed-off-by: Simon Glass <sjg@chromium.org>
* | Fix test failure caused by bad handling of ramdiskSimon Glass2014-08-28-2/+4
| | | | | | | | | | | | | | | | | | | | | | Commit e3a5bbce broke the FIT image tests by not loading a ramdisk even if a load address is provided in the FIT. The rationale was that a load address of 0 should be considered to mean 'do not load'. Add a new load operation which supports this feature, so that the ramdisk will be loaded if a non-zero load address is provided. Signed-off-by: Simon Glass <sjg@chromium.org>
* | kconfig: add CONFIG_CC_OPTIMIZE_FOR_SIZEMasahiro Yamada2014-08-28-1/+15
| | | | | | | | | | | | | | Copy the Kconfig option from "init/Kconfig" of Linux v3.16 tag and adjust the help document. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | scripts: refetch scripts/setlocalversion from Linux 3.16Masahiro Yamada2014-08-28-17/+14
| | | | | | | | | | | | | | | | Now we have CONFIG_LOCALVERSION and CONFIG_LOCALVERSION_AUTO in Kconfig so we can use scripts/setlocalversion without any adjustment. Copy it from Linux 3.16 as is. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | kconfig: add CONFIG_LOCALVERSION and CONFIG_LOCALVERSION_AUTOMasahiro Yamada2014-08-28-1/+37
| | | | | | | | | | | | | | | | | | Copy Kconfig options from "init/Kconfig" of Linux v3.16 tag and adjust some parts of the help document. Move CONFIG_SPL, CONFIG_TPL, ... etc. to "Boot images" menu. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | buildman: run genboardscfg.py all the timeMasahiro Yamada2014-08-28-6/+4
| | | | | | | | | | | | | | | | | | | | This commit makes sure boards.cfg is up to date before starting the build tests. tools/genboardscfg.py exits immediately printing "boards.cfg is up to date. Nothing to do." when boards.cfg is already new. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | MAKEALL: run genboardscfg.py all the timeMasahiro Yamada2014-08-28-7/+4
| | | | | | | | | | | | | | | | | | This commit makes sure boards.cfg is up to date before starting the build tests. tools/genboardscfg.py exits immediately printing "boards.cfg is up to date. Nothing to do." when boards.cfg is already new. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | tools/genboardscfg.py: fix a bug of MAINTAINERS handlingMasahiro Yamada2014-08-28-1/+1
| | | | | | | | | | | | | | | | | | This patch fixes a minor problem: If a block without "F: configs/*_defconfig" is followed by another block with "F: configs/*_defconfig", the maintainers from the former block are squashed into the latter. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | samsung: s5p_goni: fix: Add missing definitions for G_DNL_UMS gadgetŁukasz Majewski2014-08-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The commit (SHA1: 8fc171318e352) reintroduced correct values for vendor and product IDs required for UMS gadget to work properly either at Windows or Linux. This data was missing for GONI target, so this commit corrects this mistake. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-08-28-13/+982
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| * Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-09-13/+982
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| | * sun7i: Add bananapi boardHans de Goede2014-07-31-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Banana Pi is an A20 based development board using Raspberry Pi compatible IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi and stereo audio out + various expansion headers: http://www.lemaker.org/ Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * sunxi: HYP/non-sec: configure CNTFRQ on all CPUsMarc Zyngier2014-07-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CNTFRQ needs to be properly configured on all CPUs. Otherwise, virtual machines hoping to find valuable information on secondary CPUs will be disapointed... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: HYP/non-sec: add sun7i PSCI backendMarc Zyngier2014-07-31-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sun7i: Add support for a number of new sun7i boardsHans de Goede2014-07-31-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for boards which I own and which already have a dts file in the upstream kernel. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-11-05 23:48:59 +0000