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* pmic: pmic_pfuze100: Use a shorter name for PMIC nameFabio Estevam2014-08-08-6/+6
| | | | | | | | | | | It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already know it is a PMIC. Call it simply 'PFUZE100' instead. Cc: Tim Harvey <tharvey@gateworks.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADEDFabio Estevam2014-08-08-1/+1
| | | | | | | According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of register CCM_CIMR corresponds to bit 19 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definitionFabio Estevam2014-08-08-1/+1
| | | | | | | According to the Reference Manual the 'wb_per_at_lpm' field of register CCM_CLPCR corresponds to bit 16 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offsetFabio Estevam2014-08-08-2/+2
| | | | | | | | According to the Reference Manual the 'spdif0_clk_podf' field of register CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset definitions accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: imx-regs: Remove unused 'omux' field from iomux structFabio Estevam2014-08-08-2/+0
| | | | | | | | | | 'omux' field is not used anywhere and such layout is not valid for mx6solox. Instead of adding more ifdef's into the structure, let's simply remove this unused 'omux' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* arm: m53evk: Fix RTC bus numberMarek Vasut2014-08-08-1/+1
| | | | | | | | | A previous update to the I2C stack introduced a typo in the configuration option. Fix the typo and therefore allow the RTC to work correctly with the 'date' command again. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-08-3147/+8923
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| * ARM: HYP/non-sec: remove MIDR check to validate CBARMarc Zyngier2014-07-28-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a form of whitelist to check if we know of a CPU core and and obtain CBAR is a bit silly. It doesn't scale (how about A12, A17, as well as other I don't know about?), and is actually a property of the SoC, not the core. So either it works and everybody is happy, or it doesn't and the u-boot port to this SoC is providing the real address via a configuration option. The result of the above is that this code doesn't need to exist, is thus forcefully removed. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec/PSCI: emit DT nodesMarc Zyngier2014-07-28-2/+112
| | | | | | | | | | | | | | | | | | | | | | Generate the PSCI node in the device tree. Also add a reserve section for the "secure" code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: convert arch_fixup_memory_node to a generic FDT fixup functionMa Haijun2014-07-28-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | Some architecture needs extra device tree setup. Instead of adding yet another hook, convert arch_fixup_memory_node to be a generic FDT fixup function. [maz: collapsed 3 patches into one, rewrote commit message] Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: add the option for a second-stage monitorMarc Zyngier2014-07-28-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: add generic ARMv7 PSCI codeMarc Zyngier2014-07-28-0/+141
| | | | | | | | | | | | | | | | | | Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: allow relocation to secure RAMMarc Zyngier2014-07-28-140/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current non-sec switching code suffers from one major issue: it cannot run in secure RAM, as a large part of u-boot still needs to be run while we're switched to non-secure. This patch reworks the whole HYP/non-secure strategy by: - making sure the secure code is the *last* thing u-boot executes before entering the payload - performing an exception return from secure mode directly into the payload - allowing the code to be dynamically relocated to secure RAM before switching to non-secure. This involves quite a bit of horrible code, specially as u-boot relocation is quite primitive. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: add separate section for secure codeMarc Zyngier2014-07-28-1/+33
| | | | | | | | | | | | | | | | | | | | | | In anticipation of refactoring the HYP/non-secure code to run from secure RAM, add a new linker section that will contain that code. Nothing is using it just yet. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: add missing HYP mode constantMarc Zyngier2014-07-28-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | In order to be able to use the various mode constants (far more readable than random hex values), add the missing HYP and A values. Also update arm/lib/interrupts.c to display HYP instead of an unknown value. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: non-sec: reset CNTVOFF to zeroMarc Zyngier2014-07-28-1/+8
| | | | | | | | | | | | | | | | | | | | | | Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: add a barrier after setting SCR.NS==1Marc Zyngier2014-07-28-0/+1
| | | | | | | | | | | | | | | | A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: HYP/non-sec: move switch to non-sec to the last boot phaseMarc Zyngier2014-07-28-3/+6
| | | | | | | | | | | | | | | | | | | | | | Having the switch to non-secure in the "prep" phase is causing all kind of troubles, as that stage can be called multiple times. Instead, move the switch to non-secure to the last possible phase, when there is no turning back anymore. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-1298/+2038
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| | * ARM: omap: move board specific NAND configs out from ti_armv7_common.hpekon gupta2014-07-25-8/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves some board specific NAND configs: - FROM: generic config file 'ti_armv7_common.h' - TO: individual board config files using these configs. So that each board can independently set the value as per its design. Following configs are affected in this patch: CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand> CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon> CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon> CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon> This patch also updates documentation for few of above NAND configs. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * ARM: omap: clean redundant PISMO_xx macros used in OMAP3pekon gupta2014-07-25-99/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PISMO_xx macros were used to define 'Platform Independent Storage MOdule' related GPMC configurations. This patch - Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided by current u-boot infrastructure. - Removes unused redundant macros, which are no longer required after merging of common platform code in following commit commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform +-----------------+-----------------------------------------------------------+ | Macro | Reason for removal | +-----------------+-----------------------------------------------------------+ | PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so | | | configuring GPMC chip-select for smallest allowable | | | segment (GPMC_SIZE_16M) is enough. | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of | | | 128MB (GPMC_SIZE_128M) | +-----------------+-----------------------------------------------------------+ +-----------------+-----------------------------------------------------------+ | PISMO1_NOR | Unused Macros | | PISMO1_NAND | | | PISMO2_CS0 | | | PISMO2_CS1 | | | PISMO1_ONENAND | | | PISMO2_NAND_CS0 | | | PISMO2_NAND_CS1 | | | PISMO1_NOR_BASE | | | PISMO1_NAND_BASE| | | PISMO2_CS0_BASE | | +-----------------+-----------------------------------------------------------+ Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * ARM: omap: fix GPMC address-map size for NAND and NOR devicespekon gupta2014-07-25-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * ARM: OMAP: Fix handling of errata i727Rajendra Nayak2014-07-25-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5 ES 1.0 devices. The current revision check erroneously implements this on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance) infact causes an asynchronous abort and ends up masking it in CPSR, only to be uncovered once the kernel switches to userspace. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * board: k2e-evm: add board supportHao Zhang2014-07-25-0/+178
| | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: spl: add K2E SoC supportKhoronzhuk, Ivan2014-07-25-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone2: use CONFIG_SOC_KEYSTONE in common placesKhoronzhuk, Ivan2014-07-25-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: add MSMC cache coherency support for K2E SOCHao Zhang2014-07-25-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: clock: add K2E clock supportHao Zhang2014-07-25-6/+203
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: add K2E SoC hardware definitionsHao Zhang2014-07-25-44/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone: ddr3: move K2HK DDR3 configuration to a common fileHao Zhang2014-07-25-285/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's convenient to hold configurations for DDR3 PHY and EMIF in separate common place. This patch moves K2HK DDR3 PHY and EMIF configuration data with different rates and memory size to a common ddr3_cfg.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * configs: k2hk_evm: config: add common EVM configuration headerHao Zhang2014-07-25-244/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a common config header file for all the Keystone II EVM platforms. It combines a lot of general definitions in one file. The common header included in the EVM should be specific configuration header. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone: clock: move K2HK SoC dependent code in separate fileKhoronzhuk, Ivan2014-07-25-145/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: move K2HK board files to common KS2 board directoryHao Zhang2014-07-25-103/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves K2HK board directory to a common Keystone II board directory. The Board related common functions are moved to a common keystone board file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone2: add env option to do unitrd dt fixupMurali Karicheri2014-07-25-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With latest v3.13 kernel, unitrd dt fixup is not needed. However for older kernel versions such as v3.8/v3.10, it is needed. So to work with both, add a u-boot env variable that can be set to do dt fixup for older kernels. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * k2hk: use common KS2_ prefix for all hardware definitionsKhoronzhuk, Ivan2014-07-25-148/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone2: add possibility to turn off all dspsHao Zhang2014-07-25-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone2: move cpu_to_bus() to keystone.cHao Zhang2014-07-25-14/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: keystone_nav: make it dependent on keystone driverKhoronzhuk, Ivan2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone2: ddr: add DDR3 PHY configs updated for PG 2.0Hao Zhang2014-07-25-2/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * keystone: ddr3: add ddr3.h to hold ddr3 APIKhoronzhuk, Ivan2014-07-25-54/+76
| | | | | | | | | | | | | | | | | | | | | | | | It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: keystone2: psc: use common PSC baseKhoronzhuk, Ivan2014-07-25-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * ARM: omap: tao3530: Convert to generic boardStefan Roese2014-07-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use generic board setup functions by defining CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| | * ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.cStefan Roese2014-07-25-139/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
| | * ARM: omap: Fix GPMC init for OMAP3 platformsStefan Roese2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
| | * tricorder: convert to generic boardAndreas Bießmann2014-07-25-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Thomas Weber <thomas.weber@corscience.de>
| | * am335x_evm / gumstix pepper: Correct DDR settingsTom Rini2014-07-25-58/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-By: Ash Charles <ashcharles@gmail.com>
| | * k2hk_evm: add script to automate NAND flash processKhoronzhuk, Ivan2014-07-25-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com>
| | * keystone: add support for NAND gpheader imageKhoronzhuk, Ivan2014-07-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for NAND gpheader image. TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the nand u-boot image. So add zeros at the end of the nand gph image. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * mtd: nand: davinci: add opportunity to write keystone U-boot imageKhoronzhuk, Ivan2014-07-25-1/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone SoCs use the same NAND driver as Davinci. This patch adds opportunity to write Keystone U-boot image to NAND device using appropriate RBL ECC layout. This is needed only if RBL boots U-boot from NAND device and that's supposed that raw u-boot partition is used only for writing image. The main problem is that default Davinci ECC layout is different from Keystone RBL layout. To read U-boot image the RBL needs that image was written using RBL ECC layout. The BBT table is written using default Davinci layout and has to be updated using one. The BBT can be updated only while erasing chip or by forced bad block assigning, so erase function has to use native ecc layout in order to be able to write BBT correctly. So if we're writing to NAND U-boot address we use RBL layout for others we use default ECC layout. Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no reasons to use ECC layout commands. It was added by mistake. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * tps65218/am43xx_evm: Add power framework support to TPS65218Tom Rini2014-07-25-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | Add in an init function for the drivers/power framework so we can dump and read the registers via i2c. Cc: Łukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-07 16:52:53 +0000