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* MLK-11050 ARM: imx6: configure the PMIC_STBY_REQ pin as open drainBai Ping2015-06-05-0/+9
| | | | | | | Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11033 imx: mx7d: Update the lpddr3 script to 3.0.3 revYe.Li2015-06-04-4/+4
| | | | | | | | | | | | | | | | | | Update the DDR script for i.MX7D 12x12 LPDDR3 ARM2 board and i.MX7D 19x19 LPDDR3 ARM2 board to file "7D_lpddr3_0_3.ds5" Updated items: Changes DRAMTMG2 WR2RD from 7 to 8. Compass link for this script: http://compass.freescale.net/livelink/livelink?func=ll &objid=233861153&objAction=browse&sort=name Test results: Passed overnight test on two MX7D 12x12 LPDDR3 ARM2 board Passed overnight test on one MX7D 19x19 LPDDR3 ARM2 board Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11036 imx: mx6ul fix plugin build fail and update ddrPeng Fan2015-06-04-5/+9
| | | | | | | | | | Since directory name changed, need to change it in imximage.cfg, or we will get "Can't stat board/freescale/mx6ulevk/plugin.bin". Since this commit 7331a4cc0853722b4c3addf1927a2797f39f5de2 missed to update ddr, here update the plugin code. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11011 imx: mx6ul-14x14-evk update ddr version to 1.1Peng Fan2015-06-02-4/+4
| | | | | | | | | | | | | | | | | | | | updated DDR Script of 6UL EVK Board to avoid a calibration error when using “DDR_Stress_Tester_V1.04.exe”. Updated items: [Modified] setmem /32 0x020E027C = 0x00000008 [Modified] setmem /32 0x020E0280 = 0x00000038 [Modified] setmem /32 0x021B080C = 0x00070007 [Added ] setmem /32 0x021B0858 = 0x00000F00 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Tested on two boards, both passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11010 imx: mx7d: Fix EIMNOR lock issue on mx7d 19x19 lpddr3 boardYe.Li2015-06-01-0/+4
| | | | | | | | | | Since the flash blocks are locked at default , need to set "CONFIG_SYS_FLASH_PROTECTION" to unlock them before write/erase. The patch also add the pinmux for LBA (ADV) pin and set eimnor enabled at default. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11008 imx: HAB: Fix secure boot configuration and build issueYe.Li2015-06-01-2/+2
| | | | | | | | | | | 1. There is conflict when building secure boot, because some common codes for MPC are included by using same configuration. So modify the makefile to get rid of them. 2. The 6UL arch config is missed in hab.h. Fix this issue by using the CONFIG_ROM_UNIFIED_SECTIONS. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10981 mxc: ocotp fix hole in shadow registersPeng Fan2015-05-29-6/+76
| | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10972-2 imx: mx7dsabresd fix i2c index usagePeng Fan2015-05-26-1/+1
| | | | | | i2c_pad_info3's i2c index should 2, but not 1. Correct it. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10972-1 imx: mx7d Add SION bit for i2c pin muxPeng Fan2015-05-26-28/+28
| | | | | | Add SION bit for all i2c pin mux settings. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2015-05-25-1/+507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10956 imx: mx6ul: Change BSP name and dtb name for 14x14 packageYe.Li2015-05-25-75/+75
| | | | | | | | | | | | | | Since there is another 9x9 package for mx6ul, modify the BSP names of ddr3 arm2 board and evk board to add 14x14 package info. Also modify the loaded dtb file to align with kernel. After the change, the build target for mx6ul ddr3 arm2 board is: mx6ul_14x14_ddr3_arm2_config and the build target for mx6ul evk board is: mx6ul_14x14_evk_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10955 imx: mx7d arm2: Add NAND support for mx7d 19x19 lpddr3 arm2 boardYe.Li2015-05-25-0/+28
| | | | | | | | Add the default TSOP NAND support and build target. New build target for nand boot: mx7d_19x19_lpddr3_arm2_nand_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10546-2 imx: mx7 implement reset_miscPeng Fan2015-05-22-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress reset test, and hangs in rom code. Rom log buffer show thats wrong hab_image_entry and runs into serial download mode. Also there is no time delay reset circuit for this board. We found when disable CONFIG_VIDEO, all seems fine. Actually, only the following piece of code can make stress reset ok, " writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr); while (--timeout) { if (readl(&regs->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ) break; udelay(1); } " Here we use lcdif_power_down API which is better to shutdown lcdif same as the way used in arch_preboot_os. Implement reset_misc for mx7, since it does not hurt for others boards. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10546-1 imx: mxsfb include fb.hPeng Fan2015-05-22-1/+3
| | | | | | Include fb.h in mxsfb.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10936 imx: mx7d: Change to use bootrom_sw_info for getting boot deviceimx_3.14.38_6ul_engrYe.Li2015-05-20-60/+56
| | | | | | | | | | | | | | | | | | | | | On MX7D, boot rom can provide some boot information such as boot device, arm freq, axi freq, etc. (see the structure below) Offset Byte4 | Byte3 | Byte2 | Byte1 0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved 0x4 ARM core frequency(in Hz) 0x8 AXI bus frequency(in Hz) 0x0C DDR frequency(in Hz) 0x10 GPT1 input clock frequency(in Hz) 0x14 Reserved 0x18 0x1C The boot information can be accessed by get the pointer at 0x1E8. This patch changes the u-boot to use the new approach. When manufacture boot, the info recorded is the actual SD port, not the failed device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10931 imx: wdog: Turn off internal reset signal for mx7dYe.Li2015-05-20-0/+4
| | | | | | | Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB for mx7d. So that the warm reset is disabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10908: imx: mx6sx Add mx6sx_17x17_arm2_qspi2 configHan Xu2015-05-15-0/+7
| | | | | | This config was missed when porting to 2015.04 u-boot. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-10885 imx: mx6slevk ignore elan init when no epdc on boardPeng Fan2015-05-14-13/+21
| | | | | | | | | | | | | | | | If no epdc pannel is plugged into mx6slevk board, no need to do the elan init operation for each i2c init transfer which will slow the i2c speed. If epdc panned is plugged into mx6slevk board, all works as the original patch: "b6ba68516b681a38025252bd0ef6a6ed3e8adfa0" - "MLK-10215 Add elan init in i.MX6SL-EVK board" This patch also fix a bug that setup_elan_pads should be called in board_init, but not board_late_init where too late to setup_elan_pads. And align pad property with linux kernel, value is 0x17000. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10839: arm: imx: mx7d 19x19 lpddr3 arm2 board supportAdrian Alonso2015-05-13-2/+1072
| | | | | | | | | | | | | * Add mx7d_19x19_lpddr3_arm2 target board supprt * Enable i2c, spinor, usb, usdhc, qspi, enet, uart * Build targets mx7d_19x19_lpddr3_arm2_defconfig mx7d_19x19_lpddr3_arm2_eimnor_defconfig - Set EIMNOR settings for Intel Sibley Asynchronous mode - Set flash sector size for 256kb (erase block size) Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10884 imx: MX6SX: Fix IOMUXC GPR registers access issueYe.Li2015-05-13-6/+2
| | | | | | | | The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL, so when using this structure to access gpr registers needs to change the base address to IOMUXC_BASE_ADDR. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10873-2 imx:mx6ul removed uncompiled pmic codePeng Fan2015-05-11-8/+0
| | | | | | | This piece of code will never be compiled and used, since we use pmic framework. So remove the code block. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10873-1 imx:mx7d use pmic frameworkPeng Fan2015-05-11-93/+58
| | | | | | Use pmic framework to simplify code and make code clean. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10870 imx: mx7d: Implement to get board serial numberYe.Li2015-05-11-1/+7
| | | | | | Get the Unique ID of the chip from the fuse TESTER0 and TESTER1. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10865 imx: mx6ulevk: Add android supportYe.Li2015-05-08-0/+182
| | | | | | | | Add android features booti, fastboot and recovery to i.MX6UL EVK board. Since there is no user button on the board, we can't implement the recovery by using button. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10855 imx: mx6ulevk/ddr3_arm2: Fix bmode value for SD1 and SD2Ye.Li2015-05-07-3/+3
| | | | | | Correct USDHC Port Selection bits in bmode value for SD1 and SD2. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10852 imx: mx6ul_ddr3_arm2: Add support for NAND bootYe.Li2015-05-07-20/+27
| | | | | | | | | | | Since the NAND has two pins conflict with SD2, when NAND is enabled, we must disable SD2. So the CONFIG_SYS_FSL_USDHC_NUM needs configure to 1 and should be moved to under defining CONFIG_SYS_USE_NAND. New build target for NAND boot: mx6ul_ddr3_arm2_nand_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10841 imx: mx6ul_ddr3_arm2: Add support for WEIMNOR bootYe.Li2015-05-07-5/+17
| | | | | | | | | | Correct the EIMNOR settings to non-mux mode and set the environment variables configuration to FLASH when using WEIMNOR boot. New target is added for build WEIMNOR boot u-boot: mx6ul_ddr3_arm2_eimnor_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10740: add maximum ecc platfrom can supportHan Xu2015-05-07-1/+7
| | | | | | | | Add maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Han Xu <b45815@freescale.com> (cherry picked from commit fdc5bac6ae8b699924c4e84b86e38aa73f694827)
* MLK-10747-2 video: ipu: Enable/disable LDB_DI clock when necessaryLiu Ying2015-05-07-7/+65
| | | | | | | | This patch adds enable/disable hooks support for ldb_di[0/1] clocks and enables/disables them when necessary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 839a1da941be48baf27c9cb28939cc6b2030424a)
* MLK-10747-1 video: ipu: Build ldb_di clock relevant code only for MX6 and MX53Liu Ying2015-05-07-2/+14
| | | | | | | | The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock relevant code be built only for them. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit c0dc175a9780505ec8939bda5dda9c2ec549a7f0)
* MLK-10829-2 imx:mx6 support thermal for all mx6Peng Fan2015-05-06-14/+10
| | | | | | | | Move CONFIG_IMX_THERMAL to mx6_common.h Make CONFIG_MXC_OCOTP only depends on CONFIG_CMD_FUSE, since when THERMAL is not implemented, we may use fuse. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10829-1 imx:mx6sx correct i2c and video clock settingsPeng Fan2015-05-06-13/+3
| | | | | | | | Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx Remove duplicated mxs_set_vadcclk Correct enable_pll_video usage Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10827 imx: mx6 update thermal driver according new equationPeng Fan2015-05-06-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 – (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4445388 – (0.0016549 * Count room fuse) Offset = 3.580661 " According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10817 imx:mx6ul_ddr3_arm2 add mx6ul ddr3 arm2 board supportPeng Fan2015-05-05-0/+1762
| | | | | | | | | | | | | Add board code for mx6ul ddr3 arm2 board. QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR Add sd1, qspi and spinor boot support DDR script is 1.02 version. Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10821 imx: mx6ulevk: Add board support for mx6ulevkYe.Li2015-05-05-0/+1570
| | | | | | | | | | | Add BSP codes to support modules on the board: I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial DDR version: 1.0 Build target: mx6ulevk_config mx6ulevk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-6 net: fec: add platform check to avoid to access the reserved ↵Peng Fan2015-05-05-1/+4
| | | | | | | | | register Add platform check to avoid to access the reserved register Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-5 imx: qspi i.MX6UL needs at least 16 bytes when writePeng Fan2015-05-05-2/+2
| | | | | | i.MX6UL qspi controller also needs at least 16 bytes when writing. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-4 mxc:gpio Add MX6UL supportPeng Fan2015-05-05-0/+4
| | | | | | comment out GPIO6/7 for MX6UL Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-3 imx:mx6ul PAD_CTL_SPEED_LOW for mx6ulPeng Fan2015-05-05-1/+1
| | | | | | PAD_CTL_SPEED_LOW for mx6ul same with mx6sx. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-2 imx:mx6ul add clock supportPeng Fan2015-05-05-61/+421
| | | | | | | | | | | | add i.MX6UL clock related settings/macros/apis When using TFT43AB, its pixel size is 480x272 which needs a slow pix clock. Without apply the test_div in PLL video, we can't get the pix clock in the rate. So change the LCDIF clock calculation to use the test_div. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-1 imx:mx6 add i2c4 supportPeng Fan2015-05-05-8/+28
| | | | | | I2C4 support for i.MX Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10808-5 imx: mx6ul: Update soc relevant settingsYe.Li2015-05-05-9/+25
| | | | | | | Remove PCIe, xPU power, PL310 L2 Cache for MX6UL. Update FEC MAC address, WDOG settings, USDHC clock rate. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-4 imx: Move system counter driver to imx-commonYe.Li2015-05-04-11/+28
| | | | | | | | | | | | | Since the system counter driver will also be used by mx6ul, move this timer driver to imx-common and rename it as syscounter.c For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default). GPT timer: CONFIG_GPT_TIMER System counter timer: CONFIG_SYSCOUNTER_TIMER Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-3 imx: mx6ul: Update imx registers head fileYe.Li2015-05-04-33/+114
| | | | | | Update imx registers base address for i.MX6UL Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-2 imx: mx6ul: Add pins IOMUX head fileYe.Li2015-05-04-0/+1068
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-1 imx: mx6ul: Add i.MX6UL CPU typeYe.Li2015-05-04-2/+5
| | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime. The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value has been occupied by i.MX6D as a dummy CPU type. So we also need change i.MX6D to a invalid value 0x67. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-53 imx: update setting pmic volatagePeng Fan2015-04-29-8/+179
| | | | | | | | We should not rely on pfuze_common_init to set the voltage, may be we should remove the voltage settings in pfuze_common_init. This patch is to setting the voltages in power_init_board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-52 nand: mxs correct MXS_DMA_ALIGNMENTPeng Fan2015-04-29-1/+1
| | | | | | | | | | | | We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise we may encounter errors, " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10733 imx: imx6qpsabreauto: Update IPU QoS settingsLiu Ying2015-04-29-3/+3
| | | | | | | | | | | | | | Update IPU QoS settings from 0x007f007f to 0x77177717 according to the SoC team's recommendation. This change should be able to balance AXI ID0/2/3 priority and set AXI ID1 priority relatively lower, which matches the way we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs, IDMAC27 and IDMAC28 respectively in kernel. The specific priority values for each AXI ID are supposed to be picked for the sake of an overall good system performance. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
* MA-6580 recovery.img cannot be authenticated by HABguoyin.chen2015-04-29-9/+13
| | | | | | | | | | Remove the authentication size to be a fixed size, due to recovery.img may be much bigger than the boot.img Add signature size to boot or recovery image size, which is added by boot_signer in android build process Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit d59b24fefcd56d085c4010643ca9f6522a3cc58a)
generated by cgit v1.1 at 2024-07-15 23:23:43 +0000