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* MPC83xx, MPC85xx: compile stub cache functionStefano Babic2012-07-21-2/+2
| | | | | | | | | | | | | | | | | An empty flush_dcache_range() was added into MPC83xx and MPC85xx to work with drivers shared with other architecture. However, it is compiled only if USB is set, but it is required for other drivers (FSL_ESDHC), too. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Andy Fleming <afleming@gmail.com> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Marek Vasut <marex@denx.de> CC: Wolfgang Denk <wd@denx.de> Added MPC83xx version. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-20-64/+97
|\ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency ARM: OMAP4: PANDA: Add rest of the USB module pads to essentials arm: armv7: add compile option -mno-unaligned-access if available arm: Fix to mistake clean the memory space Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependencyFabio Estevam2012-07-20-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | Create a weak-aliased arch_cpu_init, so that we can get rid of CONFIG_ARCH_CPU_INIT and always call arch_cpu_init. This way we do not need to define CONFIG_ARCH_CPU_INIT in every board file, since arch_cpu_init() is supposed to handle common CPU level code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * ARM: OMAP4: PANDA: Add rest of the USB module pads to essentialsSRICHARAN R2012-07-20-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 1a89a217f5c5ab3645c80c1247e8911a8b5ad491 we moved most of the required pads and mux data for USB to the essential list so that later on we could NOT enable anything that wasn't essential unless otherwise configured. This was however missing a few pandaboard-specific parts which left for example USB ethernet non-functional. Tested this on OMAP4430 ES2.2, OMAP4460 ES1.1 PANDA boards. (Reworded by Tom Rini to be more precise about what the problem was) Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Gary Thomas <gary@mlbassoc.com> Tested-by: Tom Rini <trini@ti.com>
| * arm: armv7: add compile option -mno-unaligned-access if availableTetsuyuki Kobayashi2012-07-20-0/+2
| | | | | | | | | | | | | | | | | | | | Recent compiler generates unaligned memory access in armv7 default. But current U-Boot does not allow unaligned memory access, so it causes data abort exception. This patch add compile option "-mno-unaligned-access" if it is available. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Tested-by: Gary Thomas <gary@mlbassoc.com>
| * arm: Fix to mistake clean the memory spaceZhong Hongbo2012-07-20-40/+65
| | | | | | | | | | | | | | | | | | | | | | In currently, when __bss_start is equal to __bss_end__, The bss loop will clear all the things in memory space. But just only when __bss_end__ greater than __bss_start__, we do the clear bss section operation. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nds32Wolfgang Denk2012-07-20-225/+158
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nds32: nds32: split common cache access from cpu into lib Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | nds32: split common cache access from cpu into libMacpaul Lin2012-07-20-225/+158
| |/ | | | | | | | | | | | | | | | | | | | | This commit does the following updates. 1. Split the common cache access from cpu.c into lib folder. 2. Rename the following cache api to adapt common.h - dcache_flush_rang -> flush_dcache_rang - icache_inval_range -> invalidate_icache_range 3. Add invalidate_dcache_range Signed-off-by: Macpaul Lin <macpaul@gmail.com>
* | common.h: Remove include compiler.hMarek Vasut2012-07-20-2/+1
|/ | | | | | | | | | | | | Remove this as including it on global scale breaks a lot of things. This was reported by: Matthew McClintock <B29882@freescale.com> Fix found by: Tom Rini <trini@ti.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-07-20-75/+117
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: usb_storage: fix ehci driver max transfer size smsc95xx: align buffers to cache line size ehci-hcd: change debug() to printf() in case of errors usb: check return value of submit_{control, bulk}_msg usb: pass cache-aligned buffer to usb_get_descriptor() ehci-hcd: fix external buffer cache handling ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment ehci-hcd: program asynclistaddr before every transfer common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER ehci-omap: Do not call dcache_off from omap_ehci_hcd_init Signed-off-by: Wolfgang Denk <wd@denx.de>
| * usb_storage: fix ehci driver max transfer sizeStefan Herbrechtsmeier2012-07-18-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 5dd95cf93dfffa1d19a1928990852aac9f55b9d9 'usb_storage: Fix EHCI "out of buffer pointers" with CD-ROM' introduce a bug in usb_storage as it wrongly assumes that every transfer can use 4096 bytes per qt_buffer. This is wrong if the start address of the data is not page aligned to 4096 bytes and leads to 'EHCI timed out on TD' messages because of 'out of buffer pointers' in ehci_td_buffer function. The bug appears during load of a fragmented file and read from or write to an unaligned memory address. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * smsc95xx: align buffers to cache line sizeIlya Yanok2012-07-18-4/+9
| | | | | | | | | | | | | | Align buffers passed to the USB code to cache line size so they can be DMAed safely. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * ehci-hcd: change debug() to printf() in case of errorsIlya Yanok2012-07-18-3/+3
| | | | | | | | | | | | Printing message could be useful if something goes really wrong. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * usb: check return value of submit_{control, bulk}_msgIlya Yanok2012-07-18-2/+4
| | | | | | | | | | | | | | Return values of submit_{control,bulk}_msg() functions should be checked to detect possible error. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * usb: pass cache-aligned buffer to usb_get_descriptor()Ilya Yanok2012-07-18-2/+4
| | | | | | | | | | | | | | usb_get_descriptor passes it's buffer argument directly to usb_control_msg() so it has to be properly aligned/padded. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * ehci-hcd: fix external buffer cache handlingIlya Yanok2012-07-18-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done: 1. Remove useless length alignment check. We get actual transfer length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignmentTom Rini2012-07-18-30/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB spec says that 32 bytes is the minimum required alignment. However on some platforms we have a larger minimum requirement for cache coherency. In those cases, use that value rather than the USB spec minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here as we are not allowed to have tests inside of align(...). Signed-off-by: Tom Rini <trini@ti.com> [marek.vasut]: introduce some crazy macro voodoo Signed-off-by: Marek Vasut <marex@denx.de> [ilya.yanok]: moved external buffer fixes to separate patch, we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN for qh_list, qh and qtd structures to make sure they are proper aligned for both controller and cache operations. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * ehci-hcd: program asynclistaddr before every transferIlya Yanok2012-07-18-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | Move or_asynclistaddr programming to ehci_submit_async() function to make sure queue head is properly programmed before every transfer. This solves the problem with changing qh address. Also remove unneeded qh_list->qh_link reprogramming at the end of transfer. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * common.h: Introduce DEFINE_CACHE_ALIGN_BUFFERMarek Vasut2012-07-18-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | This is the out-of-function-scope counterpart of ALLOC_CACHE_ALIGN_BUFFER. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> [ilya.yanok]: added missing <linux/compiler.h> include and {DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment specification. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * ehci-omap: Do not call dcache_off from omap_ehci_hcd_initTom Rini2012-07-18-1/+0
| | | | | | | | | | | | | | | | | | This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | Merge branch 'sf' of git://git.denx.de/u-boot-blackfinWolfgang Denk2012-07-20-97/+23
|\ \ | | | | | | | | | | | | | | | | | | | | | * 'sf' of git://git.denx.de/u-boot-blackfin: sf: spansion: inline useless id defines sf: drop unused/duplicate command defines Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | sf: spansion: inline useless id definesMike Frysinger2012-07-20-22/+12
| | | | | | | | | | | | | | | | | | No need for dedicated defines when these really only get used once. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | sf: drop unused/duplicate command definesMike Frysinger2012-07-20-75/+11
| |/ | | | | | | | | | | | | In an effort to unify the spi flash drivers further, drop all the unused and/or duplicate command defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2012-07-20-4/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-net: net: link_local: fix build net: bootp: fix build Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | net: link_local: fix buildbenoit.thebaudeau@advans2012-07-19-3/+3
| | | | | | | | | | | | | | | | | | | | | Fix comment within comment build error. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
| * | net: bootp: fix buildbenoit.thebaudeau@advans2012-07-19-1/+1
| |/ | | | | | | | | | | | | Fix NetSetState function name used with CONFIG_BOOTP_MAY_FAIL. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* | tools: clean up mingw ifdefsMike Frysinger2012-07-20-8/+10
| | | | | | | | | | | | | | | | We have a header file specifically for mingw cruft, so keep it there to avoid crap spreading into the main tools. This lets our devs just worry about *nix systems. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bfin_mac: drop volatile markings on packet buffersMike Frysinger2012-07-19-2/+1
| | | | | | | | | | | | | | | | | | | | Now that common code doesn't declare these as volatile, we don't need to either anymore. This fixes the build warning: bfin_mac.c: In function 'bfin_EMAC_recv': bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: easylogo: add lzma logosMike Frysinger2012-02-03-22/+2964
|/ | | | | | | | | | The bf527-ezkit boards are getting too big to fit into their reserved flash space, so we need to use a lzma compressed logo. Since the video driver code is very similar, add lzma compressed support to all of the Blackfin video drivers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk2012-07-18-135/+166
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ipu_common: Add ldb_clk for use in parenting the pixel clockEric Nelson2012-07-10-3/+12
| | | | | | | | | | | | | | Add ldb_clk for use in parenting the pixel clock. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam2012-07-10-1/+4
| | | | | | | | | | | | Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Rename MXC_CCM_BASEFabio Estevam2012-07-10-1/+1
| | | | | | | | | | | | Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53Fabio Estevam2012-07-10-1/+4
| | | | | | | | | | | | | | The registers accessed inside clk_ipu_enable/disable are not present on MX6, so make sure they only run on MX51 and MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Only apply the erratum to MX51Fabio Estevam2012-07-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The following erratum : "ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces" only applies to mx51, so restrict its usage for this SoC only. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * video: Rename CONFIG_VIDEO_MX5Fabio Estevam2012-07-10-5/+5
| | | | | | | | | | | | Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-10-3/+14
| | | | | | | | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * common lcd: minor coding style changesNikita Kiryanov2012-07-10-121/+124
| | | | | | | | | | | | | | No functional changes Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | Merge branch 'master' of git://git.denx.de/u-boot-niosWolfgang Denk2012-07-18-15/+9
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nios: nios2: move gd and bd into BSS Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | nios2: move gd and bd into BSSThomas Chou2012-07-16-15/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Graeme Russ, move gd and bd data structrures to BSS instead of calculating the locations around the stack and heap. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | | FSL/eSDHC: enable the clock to detect the SD cardJerry Huang2012-07-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FSL low-end processors (VVN2.2), in order to detect the SD card, we should enable PEREN, HCKEN and IPGEN to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used. And when accessing to these reserved bit, no any impact happened. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | SD/MMC: check the card status during erase operationJerry Huang2012-07-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the function 'mmc_send_status' to check the card status. only when the card is ready, driver can send the next erase command to the card, otherwise, the erase will failed: => mmc erase 0 1 MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK => mmc erase 0 2 MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed 1 blocks erase: ERROR => mmc erase 0 4 MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed 1 blocks erase: ERROR Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc:fix Call mmc_init() when executing mmc_get_dev()Łukasz Majewski2012-07-13-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code adds call to mmc_init(), for partition related commands (e.g. fatls, fatinfo etc.). It is safe to call mmc_init() multiple times since mmc->has_init flag prevents from multiple initialization. The FAT related code calls get_dev high level method and then uses elements from mmc->block_dev, which is uninitialized until the mmc_init (and thereof mmc_startup) is called. This problem appears on boards, which don't use mmc as the default place for envs Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc: remove the hard setting for tran_speedJaehoon Chung2012-07-13-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_set_clock is set to the hard-coding. But i think good that use the tran_speed value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | i.MX: fsl_esdhc: allow use with cache enabled.Eric Nelson2012-07-13-1/+16
|/ / | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-07-12-36/+51
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: mx28evk: Add I2C support mxs-i2c: Fix internal address byte order mxc_i2c: remove setting speed at each start mx6qsabrelite: add i2c support mxc_i2c: specify i2c base address in config file Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | mx28evk: Add I2C supportFabio Estevam2012-07-11-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support. Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | mxs-i2c: Fix internal address byte orderTorsten Fleischer2012-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory. These devices require that the high byte of the internal address has to be written first. The mxs_i2c driver currently writes the address' low byte first. The following patch fixes the byte order of the internal address that should be written to the I2C device. Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de> CC: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc_i2c: remove setting speed at each startTroy Kisky2012-07-11-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mx6qsabrelite: add i2c supportTroy Kisky2012-07-11-0/+19
| | | | | | | | | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-09-17 18:49:28 +0000