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* env_mmc: fix buffer allocation for armv7Markus Niebel2013-10-14-5/+4
| | | | | | | | | | | | | | | | | | | | commit d196bd880347373237d73e0d115b4d51c68cf2ad adds redundand environment to mmc. The usage of malloc in env_relocate_spec triggers cache errors on armv7. Tested on a not mainlined i.MX53 board: Board: TQMa53 I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57c2d8 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f57e2d8 ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57e2e0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f5802e0 Using default environment Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
* env: dataflash: fix env_init issueBo Shen2013-10-14-32/+18
| | | | | | | | | | | | As the SPI controller is not initialized before env_init(), it causes reading env in dataflash failed. So, although saveenv() successfully, it shows warning information when reboot the system as following: *** Warning - bad CRC, using default environment Let the env_relocate() to check env CRC and import it. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: omap4: Update sdram setting for panda rev A6Dan Murphy2013-10-14-0/+4
| | | | | | | | | | OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: Dan Murphy <dmurphy@ti.com>
* am335x_evm.h: Make 'am335x_boneblack' use redundant environmentTom Rini2013-10-14-0/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* .gitignore: add auto-generated /include/[s|t]pl-autoconf.mkDaniel Schwierzeck2013-10-14-0/+2
| | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* SPDX: document dual license notationWolfgang Denk2013-10-14-0/+12
| | | | | | | | | | | | | In [1] we discussed how we should deal with dual (or, more generally, multiple) licensed files. Add this to Licenses/README so it's properly documented. [1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/166518 Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Add the word 'list' to the end of the line, per Stephen Warren's feedback] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-14-0/+1449
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-11-0/+1449
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| | * samsung: trats2: add support for new board Trats2Piotr Wilczek2013-09-25-0/+859
| | | | | | | | | | | | | | | | | | | | | | | | This patch add support for a new Samsung board Trats2. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * samsung:common:i2c: add definions for third soft I2C adapter for Trats2 boardPiotr Wilczek2013-09-25-0/+12
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * power:battery: add battery support for Trats2 boardPiotr Wilczek2013-09-25-0/+66
| | | | | | | | | | | | | | | | | | Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * drivers:power:max77693: add support for new multi function pmic max77693Piotr Wilczek2013-09-25-0/+512
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for new multi function pmic max77693. The driver is split into three modules: pmic, muic and fuelgage. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-10-14-63/+129
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| * | | cmd_ubi: add write.part command, to write a volume in multiple partsPaul Burton2013-10-09-15/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows you to write data to an UBI volume when the amount of memory available to write that data from is less than the total size of the data. For example, you may split a root filesystem UBIFS image into parts, provide the total size of the image to the first write.part command and then use multiple write.part commands to write the subsequent parts of the volume. This results in a sequence of commands akin to: ext4load mmc 0:1 0x80000000 rootfs.ubifs.0 ubi write.part 0x80000000 root 0x08000000 0x18000000 ext4load mmc 0:1 0x80000000 rootfs.ubifs.1 ubi write.part 0x80000000 root 0x08000000 ext4load mmc 0:1 0x80000000 rootfs.ubifs.2 ubi write.part 0x80000000 root 0x08000000 This would write 384MiB of data to the UBI volume 'root' whilst only requiring 128MiB of said data to be held in memory at a time. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
| * | | cmd_ubi: use int64_t volume size for 'ubi create'Paul Burton2013-10-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int64_t matches the bytes field in struct ubi_mkvol_req to which the size is assigned. With the prior signed 32 bit integer, volumes were restricted to being less than 2GiB in size. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
| * | | cmd_mtdparts: use 64 bits for flash size, partition size & offsetPaul Burton2013-10-09-28/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the 64 bit size in struct mtd_info and allows the mtdparts command to function correctly with a flash >= 4GiB. Format specifiers for size & offset are given the ll length, matching its use in drivers/mtd in absence of something like inttypes.h/PRIx64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
| * | | mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEANPaul Burton2013-10-09-12/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux modified the MTD driver interface in commit edbc4540 (with the same name as this commit). The effect is that calls to mtd_read will not return -EUCLEAN if the number of ECC-corrected bit errors is below a certain threshold, which defaults to the strength of the ECC. This allows -EUCLEAN to stop indicating "some bits were corrected" and begin indicating "a large number of bits were corrected, the data held in this region of flash may be lost soon". UBI makes use of this and when -EUCLEAN is returned from mtd_read it will move data to another block of flash. Without adopting this interface change UBI on U-boot attempts to move data between blocks every time a single bit is corrected using the ECC, which is a very common occurance on some devices. For some devices where bit errors are common enough, UBI can get stuck constantly moving data around because each block it attempts to use has a single bit error. This condition is hit when wear_leveling_worker attempts to move data from one PEB to another in response to an -EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is called to perform the data copy, and after the data is written it is read back to check its validity. If that read returns UBI_IO_BITFLIPS (in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to wear_leveling worker, which then proceeds to schedule the destination PEB for erasure. This leads to erase_worker running on the PEB, and following a successful erase wear_leveling_worker is called which begins this whole cycle all over again. The end result is that (without UBI debug output enabled) the boot appears to simply hang whilst in reality U-boot busily works away at destroying a block of the NAND flash. Debug output from this situation: UBI DBG: ensure_wear_leveling: schedule scrubbing UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083 UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027 UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096 UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083 UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192 UBI: fixable bit-flip detected at PEB 1027 UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096 UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083 UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192 UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192 UBI: fixable bit-flip detected at PEB 4083 UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0 UBI DBG: erase_worker: erase PEB 4083 EC 55 UBI DBG: sync_erase: erase PEB 4083, old EC 55 UBI DBG: do_sync_erase: erase PEB 4083 UBI DBG: sync_erase: erased PEB 4083, new EC 56 UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0 UBI DBG: ensure_wear_leveling: schedule scrubbing UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083 ... This patch adopts the interface change as in Linux commit edbc4540 in order to avoid such situations. Given that none of the drivers under drivers/mtd return -EUCLEAN, this should only affect those using software ECC. I have tested that it works on a board which is currently out of tree, but which I hope to be able to begin upstreaming soon. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | usb: Prevent using reserved registers on DM36x usbAndrew Murray2013-10-10-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this bit is reserved on the DM36x. Thus this patch ensures that the reserved bit is not accesssed. It has been observed that some USB devices will fail to enumerate with errors such as 'error in inquiry' without this patch. See http://www.ti.com/litv/pdf/sprufh9a for details. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Acked-by: Marek Vasut <marex@denx.de>
* | | | omap5_common: Re-work mmc boot to try SD and eMMC, correct root deviceTom Rini2013-10-09-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 boards may have both eMMC (on MMC2) and an SD slot (on MMC1). We Update the default bootcmd to match what happens on AM335x where we try SD first, and then eMMC. In this case however, the hardware layout used for powering both of these means that in the kernel eMMC shall be found first as it is powered by a fixed regulator and SD found second as SD is powered via the palmas which will result in deferred probing. Tested-by: Aparna Balasubramanian <aparnab@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | km/scripts: fix ramfsAndreas Huber2013-10-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | 'actual_bank' is not used anymore, instead boot_bank is used. Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
* | | | powerpc/km: drop unused CONFIG_SYS_DTT_LOW_TEMPHolger Brunck2013-10-09-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | This define is not used in u-boot code, we can drop this define safely. Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | | | km/common: switch on CMD_GREPENVHolger Brunck2013-10-09-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | | | powerpc/83xx: remove staticness for qe_iop_conf_tabHolger Brunck2013-10-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a5510058 powerpc/83xx/km: make local functions and structs static removed the staticness also from this struct. But this struct is needed in arch/powerpc/cpu/mpc83xx/cpu_init.c and declared as extern. Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | | | Merge branch 'next' of git://git.denx.de/u-boot-mpc83xxTom Rini2013-10-09-6/+11
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| * | | | powerpc/83xx/km: make local functions and structs staticHolger Brunck2013-05-21-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | powerpc/83xx/km: MV88e6122 errata fix for 1.9VHolger Brunck2013-05-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata Fix: 1.9V Output from Internal 1.8V Regulator, acc. MV-S300889-00D.pdf , clause 4.5 Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | | | da850evm.h: Always set CONFIG_CMD_SF, move to by CONFIG_SPI_FLASHTom Rini2013-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we have CONFIG_SPI_FLASH set we now require CONFIG_CMD_SF. Signed-off-by: Tom Rini <trini@ti.com>
* | | | | Revert "am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should ↵Tom Rini2013-10-08-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmcroot." Upon further inspection and review and chatting with kernel folks, what happens here is that what mmcblk# a device gets is based on probe order. So a system with an SD card inserted with place eMMC on mmcblk1, but without an SD card, it will be on mmcblk0. So U-boot can only provide a best guess. In this case, if no SD card is present, we would want to pass mmcblk0p2 still. If an SD card is present, it woudl be able to provide a uEnv.txt that would be loaded (even if the kernel is NOT there) which can still update mmcroot variable. This reverts commit 827512fb1154c05c6eb1e2259e936df55c98a535. Cc: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Tom Rini <trini@ti.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-08-1380/+363
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| * | | | socfpga: Adding pin mux handoff filesChin Liang See2013-10-07-0/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the generated pin mux configuration by Preloader Generator tool Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | | | socfpga: Adding System Manager driverChin Liang See2013-10-07-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | | | omap1510inn: arm925t: remove supportAlbert ARIBAUD2013-10-07-1348/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | | usb: Fix error handling in musb_hcd.cAndrew Murray2013-10-07-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wait_until_[rx|tx]ep_ready functions return a u8 to indicate success containing the value 0, 1 or -1. This patch changes the return type to an int to accommodate the negative return values. These functions are used in the file using calls such as if (!wait_until... Where a -1 is returned it is mishandled and treated as success instead of a CRC error. This patch addresses this. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Acked-by: Marek Vasut <marex@denx.de>
| * | | | pcm051/igep0033: Supply bd_ram_ofs for cpsw driverLars Poeschel2013-10-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 2bf36ac638ab2db9f0295aa47064976eeebf80c1 the BD ram address is not hardcoded inside cpsw driver any more. Platforms have to supply their bd_ram_ofs in the platform data to the driver. This commit does this for pcm051 and igep0033 boards. Tested-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
| * | | | ARM: IGEP0033: Update timing to run DDR at 400MHz.Enric Balletbo i Serra2013-10-07-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
| * | | | am335x_evm: Switch to zImage as default rather than uImageTom Rini2013-10-07-11/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-10-08-2318/+1696
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| * | | | spi: exynos: Support word transfersRajeshwari Shinde2013-10-08-16/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | spi: exynos: Minimise access to SPI FIFO levelRajeshwari Shinde2013-10-08-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to this register by filling up and emptying FIFOs more completely, rather than just one word each time around the inner loop. Since the rxfifo value will now likely be much greater that what we read before we fill the txfifo, we only fill the txfifo halfway. This is because if the txfifo is empty, but the rxfifo has data in it, then writing too much data to the txfifo may overflow the rxfifo as data arrives. This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | spi: exynos: Support a delay after deactivateRajeshwari Shinde2013-10-08-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For devices that need some time to react after a spi transaction finishes, add the ability to set a delay. Implement this as a delay on the first/next transaction to avoid any delay in the fairly common case where a SPI transaction is followed by other processing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | exynos: Export timer_get_us() to get microsecond timerRajeshwari Shinde2013-10-08-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function, if implemented by the board, provides a microsecond timer. The granularity may be larger than 1us if hardware does not support this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | doc: SPI: Update SPI status trackJagannadha Sutradharudu Teki2013-10-07-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated SPI/status.txt, with memory_map and TODO. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: ramtron: Remove page_size printJagannadha Sutradharudu Teki2013-10-07-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no page_size for ramtron flashes, so just print the detected flash and it's size. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Minor cleanupsJagannadha Sutradharudu Teki2013-10-07-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add spaces, tabs - Commenting. - Rearrange code. - Add static qualifier for missing func. - Remove memory_map from ramtron.c - Ramtron: spi_flash_internal.h -> sf_internal.h Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | README: qspi usecase and testing documentation.Poddar, Sourav2013-10-07-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | dra7xx_evm: add SPL API, QSPI, and serial flash supportMatt Porter2013-10-07-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | spi: add TI QSPI driverMatt Porter2013-10-07-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Add memory mapped read supportPoddar, Sourav2013-10-07-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qspi controller can have a memory mapped port which can be used for data read. Added support to enable memory mapped port read. This patch enables the following: - It enables exchange of memory map address between mtd and qspi through the introduction of "memory_map" flag. - Add support to communicate to the driver that memory mapped transfer is to be started through introduction of new flags like "SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END". This will enable the spi controller to do memory mapped configurations if required. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | armv7: hw_data: change clock divider setting.Poddar, Sourav2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | omap5: add qspi supportMatt Porter2013-10-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-11-18 22:13:22 +0000