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* cmd_zfs: use common get_device_and_partition functionRob Herring2012-09-25-97/+31
| | | | | | | | Convert zfsload and zfsls to use common device and partition parsing function. With the common function "dev:part" can come from the environment and a '-' can be used in that case. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* cmd_disk: use common get_device_and_partition functionRob Herring2012-09-25-58/+19
| | | | Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* cmd_fat: use common get_device_and_partition functionRob Herring2012-09-25-66/+34
| | | | | | | | Convert fatload, fatls, and fatinfo to use common device and partition parsing function. With the common function "dev:part" can come from the environment and a '-' can be used in that case. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* cmd_extX: use common get_device_and_partition functionRob Herring2012-09-25-190/+46
| | | | | | | | Convert ext2/4 load, ls, and write functions to use common device and partition parsing function. With the common function "dev:part" can come from the environment and a '-' can be used in that case. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ext4: remove init_fs/deinit_fsRob Herring2012-09-25-61/+8
| | | | | | | There's no real need to expose this and it can be removed by using a static allocation. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* disk/part: introduce get_device_and_partitionRob Herring2012-09-25-4/+78
| | | | | | | | | | | | All block device related commands (scsiboot, fatload, ext2ls, etc.) have simliar duplicated device and partition parsing and selection code. This adds a common function to replace various implementations. The new function has an enhancement over current versions. If no device or partition is specified on the command line, the bootdevice env variable will be used (scsiboot does this). Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* disk/part: check bootable flag for DOS partitionsRob Herring2012-09-25-2/+10
| | | | | | | Determine which partitions are bootable/active. In the partition listing, print "Boot" for partitions with the bootable/active flag set. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* combine block device load commands into common functionRob Herring2012-09-25-409/+191
| | | | | | | | All the raw block load commands duplicate the same code. Starting with the ide version as it has progress updates convert ide, usb, and scsi boot commands to all use a common version. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* disk: make get_partition_info() always available to disk.cStephen Warren2012-09-25-55/+63
| | | | | | | | | | | | | | | | | | | | | | | | Now that get_device_and_partition() always calls get_partition_info() when disk.c is compiled, we must always compile the function, rather than ifdef it away. The implementation must be conditional based on CONFIG_CMD_* etc., since that's what e.g. part_dos.c uses to ifdef out get_partition_info_dos(); CONFIG_DOS_PARTITION can be enabled even without those commands being enabled. Technically, this change is required before Rob's "disk/part: introduce get_device_and_partition" patch. However, at least when the compiler optimizer is turned on, it isn't required before then in practice, since get_device_and_partition() calls get_dev(), which is stubbed out in disk.c under exactly the same conditions that get_partition_info() is not compiled, and hence the compiler never generates code for the call to the missing function. However, in my later patch "disk: get_device_and_partition() "auto" partition and cleanup", the optimizer doesn't succeed at this, and may attempt to reference the undefined function. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* MAKEALL: fix per arch board listsAllen Martin2012-09-25-19/+15
| | | | | | | | | | | | | The LIST_arm rule included the Atmel boards twice (by virtue of including both LIST_at91 and LIST_ARM9) and was missing all the arm720t, arm946es, and arm1176 boards. Change this list to use boards_by_arch() which is less error prone. After this change "./MAKEALL arm" and "./MAKEALL -a arm" build the same boards. Also fix up some missing and duplicate boards to arm, mips, and m68k. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Tom Rini <trini@ti.com>
* ARM: arm1176: Define arch_cpu_init() at the SoC levelStephen Warren2012-09-25-8/+25
| | | | | | | | | | | | | Commit 86c6326 "ARM: arm1176: enable instruction cache in arch_cpu_init()" defined arch_cpu_init() in a file that is shared across all arm1176 SoCs. tnetv107x already implemented this function, which caused linking to break. Move the new conflicting arch_cpu_init() into arm1176/bcm2835/init.c so that it doesn't conflict; grep indicates this function is usually defined at the SoC-level, not the CPU-level, at least for ARM. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Marek Vasut <marex@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2012-09-25-2999/+2682
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| * powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPLScott Wood2012-08-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LAW init is skipped in the SPL payload because it's assumed that the SPL has taken care of it -- so make sure the SPL loads all the LAWs as is done on other boards. This bug was introduced by: commit 4589728e214958a4e6e011a081a68d360c49d7a5 Author: Kumar Gala <galak@kernel.crashing.org> Date: Fri Nov 11 08:14:53 2011 -0600 powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing LAW entries not needed during SPL phase. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * Revert "powerpc: Fix declaration type for I/O functions"Andy Fleming2012-08-23-10/+10
| | | | | | | | This reverts commit 20959471b5d07fdeb8603b918d80385aa2954711.
| * powerpc/p1_p2_rdb_pc: print -PC suffix in board nameScott Wood2012-08-23-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the -PC variants of the P1/P2 RDB boards do not print it on boot -- e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect, this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC, resulting in a board that does not boot. P1024RDB and P1025RDB are not included, as these boards apparently do not have -PC as part of their name, even though they are supported by p1_p2_rdb_pc. The P2020RDB variant covered by this is apparently P2020RDB-PCA rather than P2020RDB-PC. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: clear out TLB on bootScott Wood2012-08-23-33/+48
| | | | | | | | | | | | | | | | Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.hYork Sun2012-08-23-5/+4
| | | | | | | | | | | | | | | | | | | | Before proper environment is setup, we extract hwconfig and put it into a buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to accommodate longer string. Since this macro is used in multiple files, we move it into arch/powerpc/include/asm/config.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix interactive DDR debuggingYork Sun2012-08-23-2/+2
| | | | | | | | | | | | | | | | Add one more argument to call function readline_into_buffer(). Fix print SPD format for negative values. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fall back to raw timing for first controller onlyYork Sun2012-08-23-1/+1
| | | | | | | | | | | | | | | | Only the first DIMM of first controller should fall back to raw timing parameters if SPD is missing or corrupted. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix CAS latency calculationYork Sun2012-08-23-2/+4
| | | | | | | | | | | | | | Empty slot should be skipped when calculating CAS latency. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix bug for extended DDR timingYork Sun2012-08-23-20/+43
| | | | | | | | | | | | | | | | Faster DDR3 timing requires parameters exceeding previously defined range. Extended parameters are fixed. Added some debug messages. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleavingYork Sun2012-08-23-320/+489
| | | | | | | | | | | | | | | | Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add support for cas latency 12 and aboveYork Sun2012-08-23-7/+21
| | | | | | | | | | | | | | | | Required by JEDEC 79-3E for high speed DDR3. Also change "CSn disabled" message to debug. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add fine timing support for DDR3York Sun2012-08-23-13/+42
| | | | | | | | | | | | | | | | When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Skip zero values for DDR debug registersYork Sun2012-08-23-3/+11
| | | | | | | | | | | | | | | | | | | | | | Some debug registers have non-zero default out of reset. If software is not setting debug registers, skip writing to them to avoid unnecessary overriding. Also add debug messages for workarounds and debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: fix core id for multicore bootingYork Sun2012-08-23-6/+53
| | | | | | | | | | | | | | | | | | | | For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Added new ext fields to IFCKumar Gala2012-08-23-6/+24
| | | | | | | | | | | | | | | | | | | | In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add IFC offset for DPAA/Corenet platformsKumar Gala2012-08-23-0/+1
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add e6500 processor detectionKumar Gala2012-08-23-0/+4
| | | | | | | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: use topology registers to calculate number of coresYork Sun2012-08-23-9/+70
| | | | | | | | | | | | | | | | | | We have actual topology infomation to find out exactly which core is present. Calculate the number of cores if not specified. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add immap for topology and rcpm registersYork Sun2012-08-23-1/+87
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoCPrabhakar Kushwaha2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | Freescale's High-End SoC are going to have Integrated Flash controller (IFC)'s support. So add IFC LAW target ID support for High-End SoC or corenet SoC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx:Enable debugger support to missed e500v2 SoCPrabhakar Kushwaha2012-08-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some restrictions on external debugging (JTAG). Need to define define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be used during boot to work around the limitations. Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for debug support. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: work around erratum A004510Scott Wood2012-08-23-0/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-72/+7
| | | | | | | | | | | | | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-1971/+3
| | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: get rid of enum board_slots in P4080 MDIO driverTimur Tabi2012-08-23-40/+19
| | | | | | | | | | | | | | | | | | enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and so on. This is pointless, so remove it. Also move the lane_to_slot[] array to the top of the file so that it can be used by other functions. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * fm-eth: use fdt_status_disabled() function in ft_fixup_port()Timur Tabi2012-08-23-6/+5
| | | | | | | | | | | | | | | | We have a dedicated function for setting the node status now, so use it. Also improve a comment and fix the type of the phandle variable. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: introduce function serdes_device_from_fm_port()Timur Tabi2012-08-23-0/+33
| | | | | | | | | | | | | | | | | | In order to figure out which SerDes lane a given Fman port is connected to, we need a function that maps the fm_port namespace to the srds_prtcl namespace. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * fm-eth: add function fm_info_get_phy_address()Timur Tabi2012-08-23-0/+17
| | | | | | | | | | | | | | | | | | Function fm_info_get_phy_address() returns the PHY address for a given Fman port. This is handy when the MDIO code needs to fixup the Ethernet nodes in the device tree to point to PHY nodes for a specific PHY address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+12
| | | | | | | | | | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mpc85xx: use LCRR_DBYP define instead of raw constantPaul Gortmaker2012-08-23-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the raw value of 0x80000000 directly in the code can lead to "count the zeros" bugs like that fixed in commit 718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC") Change all existing raw values to use the symbolic value of LCRR_DBYP instead. Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * nand_spl: change out_be32 to raw_writel and depend on subsequent syncMatthew McClintock2012-08-23-73/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * nand_spl: p1023rds: wait before enabling DDR controllerMatthew McClintock2012-08-23-5/+20
| | | | | | | | | | | | | | | | We have a requirement to wait a period of time before enabling the DDR controller Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * nand_spl: update udelay for Freescale boardsMatthew McClintock2012-08-23-15/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time. Looked at reusing the u-boot udelay functions but it pulls in a lot of code and would require quite a bit of work to keep us within the very small space constrains we currently have Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/p1010rdb: nandboot: compare SVR properlyMatthew McClintock2012-08-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit This fixes the boot output to show the correct DDR bus width: 512 MiB (DDR3, 16-bit, CL=5, ECC off) instead of 512 MiB (DDR3, 32-bit, CL=5, ECC off) Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)Matthew McClintock2012-08-23-3/+4
| | | | | | | | | | | | | | | | | | | | | | There was an extra 0 in front of the value we were using to mask, remove it to improve the code. Also fix the value written to ddr_sdram_cfg to set the bus width properly to 16 bits Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * p1014rdb: set ddr bus width properly depending on SVRMatthew McClintock2012-08-23-0/+12
| | | | | | | | | | | | | | | | | | | | Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Remove P1015 and P1016 from CPU listYork Sun2012-08-23-49/+7
| | | | | | | | | | | | | | | | P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/CoreNet: add tool to support pbl image build.Shaohui Xie2012-08-23-0/+601
| | | | | | | | | | | | | | | | | | | | Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-07 21:00:02 +0000