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* hashtable: drop all non-reentrant versionsMike Frysinger2010-12-17-77/+35
| | | | | | | | | | | The non-reentrant versions of the hashtable functions operate on a single shared hashtable. So if two different people try using these funcs for two different purposes, they'll cause problems for the other. Avoid this by converting all existing hashtable consumers over to the reentrant versions and then punting the non-reentrant ones. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 74xx_7xx/mpc86xx/ppmc7xx: Fix do_reset() declarationPeter Tyser2010-12-17-7/+15
| | | | | | | | | | | | | | | | | The following commit: commit 882b7d726febe65579d6502c271412ecb05821d7 Author: Mike Frysinger <vapier@gentoo.org> Date: Wed Oct 20 03:41:17 2010 -0400 do_reset: unify duplicate prototypes missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset() functions which resulted in build errors such as: cpu.c:128: error: conflicting types for 'do_reset' include/command.h:102: error: previous declaration of 'do_reset' was here Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* PowerPC, nand_spl: Add relocation support for -fpicJoakim Tjernlund2010-12-17-3/+9
| | | | | | | | | | | By rearranging the linker script we get support for relocation of -fpic for free. Move __got2_entries outside _GOT2_TABLE_ defining scope matching the rest of PowerPC Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* PowerPC: Add relocation support for -fpicJoakim Tjernlund2010-12-17-22/+33
| | | | | | | | | By rearranging the linker script we get support for relocation of -fpic for free. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* RTC driver for PT7C4338 chip.Priyanka Jain2010-12-17-0/+145
| | | | | | | | | | | PT7C4338 chip is being manufactured by Pericom Technology Inc. It is a serial real-time clock which provides: 1)Low-power clock/calendar. 2)Programmable square-wave output. It has 56 bytes of nonvolatile RAM. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Timur Tabi <timur@freescale.com>
* mpc52xx, charon: change mtd default partitionsHeiko Schocher2010-12-17-1/+14
| | | | | | | | | | | | | New default partitions on nor flash: 640k (firmware) 1408k (kernel) 2m (initrd) 4m (small-fs) 24320k (big-fs) 256k (dts) Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc5200, tqm5200: correct MTDIDS_DEFAULT to fit with name linux assignsHeiko Schocher2010-12-17-6/+6
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'next' of git://www.denx.de/git/u-boot-cfi-flash into nextWolfgang Denk2010-12-17-3/+60
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| * cfi_flash: Add optional config register write to cfi-detectionStefan Roese2010-12-17-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the possibility to (optinally) write to the flash configuration register. The Intel style CFI chips support such a register that can be used to configure the operation mode to a non-default value. This method will be used by the t3corp board, which needs to configure the DS617 Xilinx flash for async read mode. Signed-off-by: Stefan Roese <sr@denx.de>
| * cfi_flash: Use flash_read32() in sector_erased()Stefan Roese2010-12-17-3/+3
| | | | | | | | | | | | | | | | | | | | The function sector_erased() is modified to not use pointer access, but to use the correct accessor functions. This fixes a problem on the t3corp board with the Xilinx DS617 flash chips. Here a board specific accessor function is needed to read from flash in 32bit mode. This patch enables such an operation mode. Signed-off-by: Stefan Roese <sr@denx.de>
| * cfi_flash: Fix problems with status/id read modeStefan Roese2010-12-17-0/+12
| | | | | | | | | | | | | | | | | | This patch adds some calls to set the flash chip in the read-status- register- or read-id-mode before the corresponding register is read back. This problem was detected while porting the common CFI driver to support the Xilinx DS617 flash chips. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'next' of git://www.denx.de/git/u-boot-ppc4xx into nextWolfgang Denk2010-12-17-604/+142
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| * | xilinx-ppc4xx-generic: Use common u-boot.ldsRicardo Ribalda Delgado2010-12-17-559/+26
| | | | | | | | | | | | | | | | | | | | | Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx/POST: Change ethernet test loop count to a default of 10Stefan Roese2010-12-17-15/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the PPC4xx ethernet POST loop test count from currently 192 (256 - 64) to a default of 10. While doing this the max frame size is increased. Each loop run uses a different frame size, starting with a max of 1514 bytes, down to 64. The default loop count of 10 can be overriden using CONFIG_SYS_POST_ETH_LOOPS in the board config header. The TEST_NUM loop has been removed as it was never used. The main reason for this change is to reduce the boot time on boards using this POST test, like the lwmon5 board. This change reduces the boot time by about 600ms on the lwmon5 board. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
| * | ppc4xx: Update lwmon5 board supportStefan Roese2010-12-17-12/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the following changes for the lwmon5 board support: - Enable cache in SDRAM - Use common EHCI driver instead of the PPC4xx specific OHCI driver This can be done since only high-speed devices are connected. - Remove cached TLB entry again after ECC setup - Use correct define for cache enabling (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE) - Enable FIT image support Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Clarify comment about boot chip-select in start.SStefan Roese2010-12-17-12/+14
| | | | | | | | | | | | | | | | | | | | | Ths old comment was quite screwed up. Replace it with a new version that should be a bit more descriptive. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: t3corp: Add support for the Xilinx DS617 flash chipStefan Roese2010-12-17-6/+50
| |/ | | | | | | | | | | | | | | | | | | | | | | The t3corp board has an Xilinx DS617 flash chip connected to the onboard FPGA. This patch adds support for these chips. Board specific flash accessor functions are needed, since the chips can only be read correctly in 16bit mode. Additionally the FPGA chip-selects are configured for device-paced transfers (ready is enabled). Signed-off-by: Stefan Roese <sr@denx.de>
* | sf: winbond: add support for W25Q16/32/128 partsWojtek Skulski2010-12-17-10/+29
| | | | | | | | | | | | | | While we're here, cut out the useless id defines too. Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | sf: new driver for EON devicesChong Huang2010-12-17-0/+280
|/ | | | | | Signed-off-by: Chong Huang <chuang@ucrobotics.com> Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* powerpc/nand spl: link libgccScott Wood2010-12-16-8/+8
| | | | | | | | | | | | | | | | Recent GCC (4.4+) performs out-of-line epilogues in some cases, when optimizing for size. It causes a link error for _restgpr_30_x (and similar) if libgcc is not linked. It actually increases size with very small binaries, due to the fixed size of the out-of-line code, and not having any functions that actually need to restore more than 2 or 3 registers. But I don't see a way to turn it off, other than asking GCC to optimize for speed -- which may also increase size for some boards. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* MAINTAINERS: Transfer openrd_base maintainership to Prafulla WadaskarSimon Kagstrom2010-12-16-4/+1
| | | | Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Armada100: Add Board Support for Marvell Aspenite-DBPrafulla Wadaskar2010-12-16-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with * Processor upto 1.2GHz * Parallel 1Gb x8 DDR2-1066 MHz * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR * Footprints for eMMC/eSD NAND & MMC x8 card * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket * SEAF memory board, subset of PISMO2 With Peripherals: * 4.3” WVGA 24-bit LCD * Audio codecs (AC97 & I2S), TSI * VGA camera * Video in via 3 RCA jacks, and HDMI type C out * Marvell 88W8688 802.11bg/BT module * GPS RF IC * Dual analog mics & speakers, headset jack, LED, ambient light sensor * USB2.0 HS host (A), OTG (micro AB) * FE PHY, PCIE Mini Card slot * GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR This patch adds basic board support with DRAM and UART functionality The patch is tested for boot from DRAM using XDB Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* mv-common.h: Add support for ARMADA100 PlatformsPrafulla Wadaskar2010-12-16-16/+50
| | | | | | | This patch adds commonly used macros for ARMADA100 based baords, Also some code reshuffled and updated for typos and comments Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Serial: Add UART support for Marvell ARMADA 100 SoCs.Prafulla Wadaskar2010-12-16-2/+3
| | | | | | | | ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macroPrafulla Wadaskar2010-12-16-2/+6
| | | | | | | | | | On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* add Multi Function Pin configuration support for ARMADA100Prafulla Wadaskar2010-12-16-0/+67
| | | | | | This patch adds the support MFP support for Marvell ARMADA100 SoCs Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* gpio: Add Multi-Function-Pin configuration driver for Marvell SoCsPrafulla Wadaskar2010-12-16-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* arm: Add Support for Marvell ARMADA 100 Familiy SoCsPrafulla Wadaskar2010-12-16-0/+650
| | | | | | | | | | | | | | | | | | | ARMADA 100 Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/applications/armada_100 SoC versions Supported: 1) ARMADA168/88AP168 (Aspen P) 2) ARMADA166/88AP166 (Aspen M) 3) ARMADA162/88AP162 (Aspen L) Contributors: Eric Miao <eric.y.miao@gmail.com> Lei Wen <leiwen@marvell.com> Mahavir Jain <mjain@marvell.com> Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'master' of ../master into nextWolfgang Denk2010-12-16-663/+1638
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| * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-12-16-6/+45
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| | * pm9261: enable cache commandAsen Dimov2010-12-16-0/+1
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| | * pm9261: ARM relocation supportAsen Dimov2010-12-16-2/+14
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| | * pm9263: enable cache commandAsen Dimov2010-12-16-0/+1
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| | * pm9263: ARM relocation supportAsen Dimov2010-12-16-2/+14
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| | * pm9g45: enable cache commandAsen Dimov2010-12-16-0/+1
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| | * pm9g45: ARM relocation supportAsen Dimov2010-12-16-2/+14
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| * | ppc4xx: Fix missing linker scripts for partial linkingStefan Roese2010-12-15-80/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the acadia_nand and kilauea_nand linker scripts which have been missing in commit ee8028b7 [ppc4xx: Cleanup for partial linking and --gc-sections] Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bernhard Weirich <Bernhard.Weirich@riedel.net>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-12-14-6/+6
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| | * | mpc83xx: fix pcie enumerationBaidu Boy2010-12-13-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix a problem for the pcie enumeration for mpc83xx cpus. Without this we will not get correct value in hose->regions[...]. The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed. Because we will use this pointer as a parameter to call function mpc83xx_pcie_register_hose(). Signed-off-by: Baidu Boy <liucai.lfn@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-12-14-86/+66
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| | * | ARM: */start.S: use canonical asm syntaxWolfgang Denk2010-12-13-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | Make code build with older tool chains. Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | omap3: emif|sdrc: use a single global data defineNishanth Menon2010-12-11-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DECLARE_GLOBAL_DATA_PTR declarations in functions are inherently troublesome with various compilers (e.g. gcc 4.5) Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | OMAP: Timer: Replace bss variable by gdDirk Behme2010-12-11-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss values in the OMAP timer driver. The usage of bss values in drivers before initialisation of bss is forbidden. In that special case some data in .rel.dyn gets corrupted. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: John Rigby <john.rigby@linaro.org> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | DaVinci DM6446: Config UpdateSandeep Paulraj2010-12-11-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DM6446 does not build due to the ARM relocation patch. Also the board does not build in the NOR mode. Changed default to NAND to ensure no build failure. While at it removed CONFIG_CMD_KGDB Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | davinci: Rewrite timer.c to use tbl/tbu emulation variables in gdNick Thompson2010-12-11-49/+28
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change allows the davinci timer functions to be used before relocation since it avoids using static variables prior to BSS being made available. The code is based on that used in the at91 timers, modified to use a davinci specific hardware timer. It also maintains reset_timer() to allow deprecated timer usage to continue to work (for example, in nand_base.c) Signed-off-by: Nick Thompson <nick.thompson@ge.com> Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Tested-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | p1022ds: fix switching of DIU/LBC signalsTimur Tabi2010-12-13-10/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the P1022, the pins which drive the video display (DIU) are muxed with the local bus controller (LBC), so if the DIU is active, the pins need to be temporarily muxed to LBC whenever accessing NOR flash. The code which handled this transition is checking and changing the wrong bits in PMUXCR. Also add a follow-up read after a write to NOR flash if we're going to mux back to DIU after the write, as described in the P1022 RM. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controllerP.V.Suresh2010-12-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC host controller reset results in clearing of snoop bit also. This patch sets the SNOOP bit after the completion of host controller reset. Without this patch mmc reads are not consistent. Signed-off-by: P.V.Suresh <pala@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_upm: Add MxMR/MDR synchronizationJohn Schmoller2010-12-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Freescale reference manuals (eg section "13.4.4.2 Programming the UPMs" of the P4080 Reference Manual): "Since the result of any update to the MxMR/MDR register must be in effect before the dummy read or write to the UPM region, a write to MxMR/MDR should be followed immediately by a read of MxMR/MDR." The UPM on a custom P4080-based board did not work without performing a read of MxMR/MDR after a write. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | tsec: Revert to setting TBICR_ANEG_ENABLE by default for SGMIIKumar Gala2010-12-13-13/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit: commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4 Author: Peter Tyser <ptyser@xes-inc.com> Date: Tue Nov 3 17:52:07 2009 -0600 tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode Removed setting Auto-Neg by default, however this is believed to be proper default configuration for initialization of the TBI interface. Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require Auto-Neg to be disabled to function properly. This addresses a breakage on the P2020 DS & MPC8572 DS boards when used with an SGMII riser card. We also remove setting CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the default setting is sufficient for them. Additionally, we clean up the code a bit to remove an unnecessary second define. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-12-09-33/+102
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