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* serial: zynq: Remove unused #definesSoren Brinkmann2013-12-02-4/+0
| | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: trini, uboot
* Prepare v2014.01-rc1Tom Rini2013-11-25-3/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'sandbox1' of http://git.denx.de/u-boot-x86Tom Rini2013-11-25-15/+24
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| * sandbox: Make map_to_sysmem() use a constant pointerSimon Glass2013-11-21-2/+2
| | | | | | | | | | | | | | Very often a constant pointer is passed to this function, so we should declare this, since map_to_sysmem() does not change the pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Correct data sizes and printf() strings in fdtdec.cSimon Glass2013-11-21-4/+4
| | | | | | | | | | | | | | | | | | | | There are a few wwrnings in this file when building for sandbox. Addresses coming from the device tree need to be treated as ulong as elsewhere in U-Boot and we must use map_sysmem() to convert to a pointer when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
| * sandbox: config: Don't use 64-bit physical memorySimon Glass2013-11-21-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Sandbox uses an emulated memory map which is quite small. We don't need the CONFIG_PHYS_64BIT option since we can address memory with a 32-bit offset into our ram_buf. Adjust the phys_addr_t and phys_size_t types accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
| * sandbox: Use system headers first for sandbox's os.cSimon Glass2013-11-21-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | This file must be compiled with system headers, even if U-Boot has headers of the same name. The existing solution for this is good enough for libfdt, but fails when we have headers like stdint.h in U-Boot. Use -idirafter instead of -I, and remove the -nostdinc and other things that we don't want for this file. The best way to do this is to keep a copy of the original flags, rather than trying to filter them later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Use uint64_t instead of u64 for timeSimon Glass2013-11-21-2/+5
| | | | | | | | | | | | | | | | The uint64_t type is defined in linux/types.h, so is safer than u64, which is not actually a Linux type. Change-Id: Ifc9a369e6543250c49117b8d3cb3a676eee43e04 Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2013-11-25-386/+727
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| * | net: rtl8169: Add support for RTL8168d/8111dThierry Reding2013-11-22-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with the existing driver, except that it uses BAR2 instead of BAR1 for the I/O memory region. Using this patch I can use the PCIe ethernet interface on the CompuLab Trimslice to boot from the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276477
| * | net: rtl8169: Improve cache maintenanceThierry Reding2013-11-22-8/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly calling the low-level invalidate_dcache_range() and flush_cache() functions, provide thin wrappers that take into account alignment requirements. While at it, fix a case where the cache was flushed but should have been invalidated, two cases where the buffer data was flushed instead of the descriptor and a missing cache invalidation before reading the packet data that the NIC just wrote to memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276474
| * | net: zynq_gem: Add d-cache supportSrikanth Thokala2013-11-22-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | | | | | | | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | net: dm9000: random mac address supportAndrew Ruder2013-11-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random (and valid) locally administered MAC address that allows the system to network boot until a real MAC address can be configured. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
| * | drivers/net/e1000: Introduce CONFIG_E1000_NO_NVMRojhalat Ibrahim2013-11-22-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The e1000 driver expects to always have some kind of non-volatile memory attached directly to the ethernet controller chip. This means that I would have to add an additional separate flash chip to my custom board just to store essentially the MAC address. Since I don't want to do that, this patch introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables all accesses to the NVM. I have tested the patch with a 82574 controller. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
| * | net: tftpsrv: Get correct client MAC addressAndrew Ruder2013-11-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NetServerEther was not being cleared in the tftp server code, so the destination MAC address would be whatever the last destination MAC address was. Scenario: U-Boot: dhcp tftpsrv Host: Send device WRQ Device: Responds with ACK to dhcp server mac address with host ip address By clearing NetServerEther, we force a lookup of the host MAC address to go with the associated host IP. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
| * | net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
| * | net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
| * | net: tsec: Fix mac addr setup portability, cleanupClaudiu Manoil2013-11-22-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: tsec: Use portable regs type (uint->u32)Claudiu Manoil2013-11-22-141/+139
| | | | | | | | | | | | | | | | | | | | | | | | Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: tsec: Use portable types and accessors for BDsClaudiu Manoil2013-11-22-54/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the buffer descriptor (BD) fields cannot be correctly accessed by a little endian processor. This patch fixes the issue by making the access of BDs to be portable among different cpu architectures. Use portable data types for the Rx/Tx buffer descriptor fields. Use portable I/O accessors to insure that the big endian BDs are correctly accessed by little endian cpus too, and to insure proper sync with the H/W. Removed the redundant RTXBD "volatile" type, as proper synchronization around BD data accesses is provided by the I/O accessors now. The "sparse" tool was also used to verify the correctness of these changes. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: tsec: Fix CamelCase issues around BD codeClaudiu Manoil2013-11-22-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | Fix bufPtr and the rxIdx/ txIdx occurrences to solve the related checkpatch warnings for the coming patches. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: fsl_mdio: Fix warnings for __iomem pointersClaudiu Manoil2013-11-22-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. E.g.: fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different address spaces) fsl_mdio.c:34:19: expected unsigned int volatile [noderef] <asn:2>*addr fsl_mdio.c:34:19: got unsigned int *<noident> [...] tsec.c:91:35: warning: incorrect type in argument 1 (different address spaces) tsec.c:91:35: expected struct tsec_mii_mng *phyregs tsec.c:91:35: got struct tsec_mii_mng [noderef] <asn:2>*phyregs_sgmii [...] tsec.c:680:19: warning: incorrect type in assignment (different address spaces) tsec.c:680:19: expected struct tsec_mii_mng *regs tsec.c:680:19: got struct tsec_mii_mng [noderef] <asn:2>*<noident> [...] Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: tsec: Cleanup tsec regs init and fix __iomem warnsClaudiu Manoil2013-11-22-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove tsec_t typedef. Define macros as getters of tsec and mdio register memory regions, for consistent initialization of various 'regs' fields and also to manage overly long initialization lines. Use the __iomem address space marker to address sparse warnings in tsec.c where IO accessors are used, like: tsec.c:394:19: warning: incorrect type in argument 1 (different address spaces) tsec.c:394:19: expected unsigned int volatile [noderef] <asn:2>*addr tsec.c:394:19: got unsigned int *<noident> [...] Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | net: tsec: Fix priv pointer in tsec_mcast_addr()Claudiu Manoil2013-11-22-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Access to privlist[1] (hardcoded referece to the 2nd tsec's priv area) is neither correct nor does it make sense in the current context. Each tsec dev has access to its own priv instance only, and hence to its own set of group address registers (GADDR) to filter multicast addresses. This fix leads to removal of the unused (faulty) privlist[] and related global static vars. Note that mcast() can be called only after eth_device allocation and init, and hence after priv area allocation, so dev->priv is correctly initialized upon mcast() call. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 278990
| * | net: tsec: Fix and cleanup tsec_mcast_addr()Claudiu Manoil2013-11-22-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several implementation issues for tsec_mcast_addr() addressed by this patch: * unmanaged, not portable r/w access to registers; fixed with setbits_be32()/ clrbits_be32() * use of volatile pointers * unnecessary forced cast to u8 for the ether_crc() result * removed redundant parens * corrected some comment slips Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 279000
| * | net: Fix mcast function pointer prototypeClaudiu Manoil2013-11-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compiler warnings when activating CONFIG_MCAST_TFTP: tsec.c: In function 'tsec_mcast_addr': tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer from integer without a cast [enabled by default] In file included from /work/u-boot-net/include/common.h:874:0, from tsec.c:15: /work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned char *' but argument is of type 'u8' tsec.c: In function 'tsec_initialize': tsec.c:646:13: warning: assignment from incompatible pointer type [enabled by default] eth.c: In function 'eth_mcast_join': eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes integer from pointer without a cast [enabled by default] eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *' In the eth_mcast_join() implementation, eth_current->mcast() takes a u8 pointer to the multicast mac address and not a ip address value as implied by its prototype. Fix parameter type mismatch for tsec_macst_addr() (tsec.c): ether_crc() takes a u8 pointer not a u8 value. mcast() is given a u8 pointer to the multicats mac address. Update parameter type for the rest of mcast() instances. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 278989
| * | net: designware: Fix alignment of buffer descriptorsAlexey Brodkin2013-11-22-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 16-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 16-byte (128-bit) aligned. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Patch: 277902
| * | net: designware: Respect "bus mode" register contents on SW resetAlexey Brodkin2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "bus mode" register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with "0") I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Vipin Kumar <vipin.kumar@st.com> Patch: 277864
| * | net: sh-eth: Add support R8A7791Nobuhiro Iwamatsu2013-11-22-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | R8A7791 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Joe Hershberger <joe.hershberger@gmail.com>
| * | net, phy: fix AR8031 phy_maskHeiko Schocher2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944
| * | net: rtl8169: Add support for RTL8168evl/8111evlThierry Reding2013-11-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with other RTL8168 chips and can be found on the NVIDIA Cardhu and Beaver boards. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276475
| * | net: rtl8169: Fix format stringThierry Reding2013-11-22-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | currticks() is defined as get_timer(0), which returns an unsigned long, so use %lu instead of %d to print the result. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276473
| * | net: add support for extended registers to mdio commandStefano Babic2013-11-22-16/+59
| | | | | | | | | | | | | | | | | | | | | | | | Some phys (Micrel) have additional registers that can be accessed using a special sequence. This patch allows to use standard "mdio" command to accesss these registers. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | net: add function to read/write extended registers in Micrel PhyStefano Babic2013-11-22-0/+32
| | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | net: add extended function to phy APIStefano Babic2013-11-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Some phys (Micrel) has extended registers that must be accessed in a special way. Add pointers to the phy driver structure to allow to use these functions with mdio command. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | net: fix mask for phy Micrel KSZ9031Stefano Babic2013-11-22-1/+1
| | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | phy: add missing constants for Micrel KSZ9031Stefano Babic2013-11-22-0/+5
| | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is ↵Bhupesh Sharma2013-11-22-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | detected The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following method to determine which driver is to be loaded for a particular PHY module: list_for_each(entry, &phy_drivers) { drv = list_entry(entry, struct phy_driver, list); if ((drv->uid & drv->mask) == (phy_id & drv->mask)) return drv; } This means that a drv->mask of 0xfffff0 will return incorrect phy driver for the logic above, even if the drv->uid is anything other than something ending with a 0x0. For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then the phy driver selected will always be RTL8211B even though the underlying phy connected on the board is a 8211E module. This patch fixes this issue. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | net: phy/vitesse: Add support for VSC8514 phy moduleArpit Goel2013-11-22-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for VSC8514 PHY module which can be found on Freescale's T1040RDB boards. Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | net: sh-eth: Add support R8A7790Nobuhiro Iwamatsu2013-11-22-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | R8A7790 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7790. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | net: sh-eth: Add invalidate cache control for rmobile (ARM SoC)Nobuhiro Iwamatsu2013-11-22-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | The sh-eth of rmobile needs to use invalidate_cache* function. This patch adds invalidate_cache* function. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Patch: 268948
| * | net: sh-eth: Add control for padding size of packet descriptorNobuhiro Iwamatsu2013-11-22-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | sh-eth can change the alignment size of a packet descriptor according to BUS size. This patch adds this function. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | net: sh-eth: Change cache API of SHNobuhiro Iwamatsu2013-11-22-1/+2
| | | | | | | | | | | | | | | | | | | | | The cache API of SH was changed from dcache_wback_range to flush_dcache_range. sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | NET: mvgbe: avoid unused variable warning when used without phylib supportSascha Silbe2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Avoid a recently introduced unused variable warning for boards that use mvgbe but not phylib. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de> Patch: 266334
| * | net: trivial: Fix typos in mii field descriptionsStephan Bauroth2013-11-22-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Stephan Bauroth <stephan.bauroth@iav.de> Patch: 265707
| * | phylib: update atheros ar803x phyShengzhou Liu2013-11-22-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | net: tftp: Make sure timeout will not effect wrap offsetrockly2013-11-22-1/+1
| |/ | | | | | | | | | | | | | | | | | | When the block 0 store to the memory of client and timeout at this moment. Because of no ACK packet, the server will send block 0 again, if this client reconnect to the server at this time, TftpBlockWrapOffset will become larger than it should be. Signed-off-by: Rockly <rocklygnome@gmail.com> Patch: 264417
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-220/+532
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