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* x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-06-0/+1
| | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add System Memory Controller supportBin Meng2015-02-06-0/+3210
| | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add utility codes needed for MRCBin Meng2015-02-06-0/+2068
| | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-06-0/+391
| | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Bypass TSC calibrationBin Meng2015-02-06-0/+5
| | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Allow overriding TSC_FREQ_IN_MHZBin Meng2015-02-06-20/+20
| | | | | | | | We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable the Intel quark/galileo buildBin Meng2015-02-06-0/+18
| | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add basic Intel Galileo board supportBin Meng2015-02-06-0/+165
| | | | | | | | | New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add basic Intel Quark processor supportBin Meng2015-02-06-0/+295
| | | | | | | | Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add Cache-As-RAM initializationBin Meng2015-02-06-0/+105
| | | | | | | | | Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Define macros for pci configuration space accessBin Meng2015-02-06-7/+13
| | | | | | | | | Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add routines to access message bus registersBin Meng2015-02-06-0/+183
| | | | | | | | | | | In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add header files for Intel Quark SoC definesBin Meng2015-02-06-0/+68
| | | | | | | | device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove CONFIG_SATA_INTEL from x86-common.hBin Meng2015-02-06-1/+0
| | | | | | | CONFIG_SATA_INTEL is not referenced anywhere, so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-7/+4036
| | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some documentation on how to port U-Boot on x86Simon Glass2015-02-06-0/+64
| | | | | | | | Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Enable bootstage featuresSimon Glass2015-02-06-0/+3
| | | | | | | | Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* scsi: bootstage: Measure time taken to scan the busSimon Glass2015-02-06-0/+3
| | | | | | | | | On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spi: Support ValleyView in ICH SPI driverSimon Glass2015-02-06-20/+47
| | | | | | | | The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow a UART to be set up before the FSP is readySimon Glass2015-02-06-0/+7
| | | | | | | | | Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-06-38/+38
| | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unnecessary casts and fix comment typosSimon Glass2015-02-06-5/+5
| | | | | | | Tidy up the FSP support code a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mmc: Move common FSP functions into a common fileSimon Glass2015-02-06-72/+116
| | | | | | | | | | | | Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make CAR and DRAM FSP code commonSimon Glass2015-02-05-1/+3
| | | | | | | | | For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Adjust the FSP types slightlySimon Glass2015-02-05-7/+9
| | | | | | | | | | To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage to two API functions which use that convention. UPD_TERMINATOR is common so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common FSP code into a common locationSimon Glass2015-02-05-8/+16
| | | | | | Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: bootstage: Add time measurement for vesa start-upSimon Glass2015-02-05-0/+2
| | | | | | | | Since we must run a PCI BIOS ROM, and this can take a calamitous amount of time, measure it using bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-05-13/+43
| | | | | | | | If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-05-4/+17
| | | | | | | | | This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to enabling building a ROM fileSimon Glass2015-02-05-6/+9
| | | | | | | | | | | Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built. We cannot do this by default since it requires binary blobs. Without these the build will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* usb: pci: Add XHCI driver for PCISimon Glass2015-02-05-0/+61
| | | | | | | | Add a driver which locates the available XHCI controllers on the PCI bus and makes them available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* usb: pci: Use pci_find_class() to find the deviceSimon Glass2015-02-05-52/+1
| | | | | | | Use the new utility function instead of local code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Enable video for Minnowboard MaxSimon Glass2015-02-05-0/+1
| | | | | | | This board uses a new PCI ID. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Add PCI IDs for Minnowboard MaxSimon Glass2015-02-05-0/+5
| | | | | | | This board includes a few IDs we have not seen before. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add a function to find a device by classSimon Glass2015-02-05-2/+44
| | | | | | | | There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Enhance the microcode tool to support header files as inputSimon Glass2015-02-05-20/+70
| | | | | | | | | Sometimes microcode is delivered as a header file. Allow the tool to support this as well as collecting multiple microcode blocks into a single update. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini2015-02-04-25/+1254
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| * ubifs: Enable journal replay during mountAnton Habegger2015-01-29-14/+978
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ubifs_replay_journal during mount_ubifs, which was disabled before. This commit fix an issue with unrecoverable ubifs volumes after power cut. Therefor the gc.c is imported now from 1860e37 Linux 3.15 hs: added SPDX-License-Identifier for fs/ubifs/gc.c Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
| * ubifs: Import atomic_long operations from LinuxAnton Habegger2015-01-28-11/+268
| | | | | | | | | | | | | | | | | | | | This commit is a preperation for a subsequent UBIFS commit which needs atomic_long operations. Therefor "include/asm-generic/atomic-long.h" is imported from 1860e37 Linux 3.15 Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
| * ubi: reset mtd_devs when ubi part failHeiko Schocher2015-01-28-0/+8
| | | | | | | | | | | | | | if "ubi part" fails, reset also mtd_devs to 0, as further "ubi part" would use wrong mtd_devs. Signed-off-by: Heiko Schocher <hs@denx.de>
* | Prepare v2015.04-rc1Tom Rini2015-02-02-2/+2
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-02-02-72/+252
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| * | OMAP3: igep00x0: Fix boot hang and add support for status LED.Enric Balletbo i Serra2015-01-29-25/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the STATUS_LED APIs for indicating a boot progress instead of show_boot_progress. This patch also fixes a problem introduced with commit b3f4ca1135 (dm: omap3: Move to driver model for GPIO and serial). After that commit the board doesn't boot. Looks like the problem is the gpio_request call inside the function show_boot_progress. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
| * | davinci: Do not duplicate setting of gdTom Rini2015-01-29-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In f0c3a6c we stopped setting gd in board_init_f, but later had to revert to due problems on certain platforms. As davinci does not look to have these problems, we can drop the setting here and rely upon crt0.S to do it. Cc: Peter Howard <pjh@northern-ridge.com.au> Signed-off-by: Tom Rini <trini@ti.com>
| * | omap3: add some MUX definitions for upcoming cairoAlbert ARIBAUD \(3ADEV\)2015-01-29-2/+49
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | omap3: mmc: add 1.8v bias setting for MMC1Albert ARIBAUD \(3ADEV\)2015-01-29-0/+5
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | omap3: add SDRC settings for Samsung K4X51163PGAlbert ARIBAUD \(3ADEV\)2015-01-29-0/+43
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)2015-01-29-1/+6
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | | | | | | | | | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | Nokia RX-51: Use generic boardPali Rohár2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine. There is no visible difference between legacy and generic board code. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz>
generated by cgit v1.1 at 2024-07-16 04:54:20 +0000